公开(公告)号：US06753182B1

公开(公告)日：2004-06-22

申请号：US08780449

申请日：1997-01-08

Applicant: Prakash G. Kadkade ,  Christopher B. Bare ,  Barbara Schnabel-Preikstas ,  Bin Yu

Inventor： Prakash G. Kadkade ,  Christopher B. Bare ,  Barbara Schnabel-Preikstas ,  Bin Yu

IPC: C12N104

CPC classification number: A01N3/00

Abstract: Methods are provided for cryopreserving plant cells and to methods for recovering viable plant cells from long or short term cryopreservation. Plant cells to be cryopreserved can be grown in culture and pretreated with a solution containing an cryorotective agent and a stabilizer. Pretreated cells are acclimated to a reduced temperature and loaded with a cryoprotective agent such as DMSO, propylene glycol or polyethylene glycol. Loaded cells are incubated with a vitrification solution which, for example, comprises a solution with a high concentration of the cryoprotective agent. Vitrified cells retain less than about 20% water content and can be frozen at cryopreservation temperatures for long periods of time without significantly altering the genotypic or phenotypic character of the cells. Plant cells may also be cryopreserved by lyophilizing cells to a preferable water content of about 40% to about 60% by weight prior to exposure to a vitrification solution or loading agent. The combination of lyophilization and vitrification or loading removes about 75% to about 95% of the plant cell's water. Cells can be successfully cryopreserved for long periods of time and viably recovered. Also provided are methods for the recovery of viable plant cells from cryopreservation. Cells are thawed to about room temperature and incubated in medium containing, a cryoprotective agent and a stabilizer. The cryoprotective agent is removed and the cells successfully incubated and recovered in liquid or semi-solid growth medium.

Abstract translation: 提供用于冷冻保存植物细胞的方法和用于从长期或短期冷冻保存中回收活的植物细胞的方法。 待冷冻保存的植物细胞可以在培养物中生长并用含有冷冻保护剂和稳定剂的溶液预处理。 预处理的细胞适应于降低的温度，并加载冷冻保护剂如DMSO，丙二醇或聚乙二醇。 将加载的细胞与玻璃化溶液一起孵育，所述玻璃化溶液例如包含具有高浓度冷冻保护剂的溶液。 玻璃化细胞保留少于约20％的水含量，并且可以在冷冻保存温度下长时间冷冻，而不显着改变细胞的基因型或表型特征。 在暴露于玻璃化溶液或加载剂之前，植物细胞还可以通过冻干细胞冷冻保存至约40％至约60％重量的优选水含量。 冷冻干燥和玻璃化或加载的组合去除植物细胞水的约75％至约95％。 细胞可以成功地冷冻保存长时间，有效地恢复。 还提供了从冷冻保存中回收活的植物细胞的方法。 将细胞解冻至约室温，并在含有冷冻保护剂和稳定剂的培养基中孵育。 除去冷冻保护剂，并将细胞在液体或半固体生长培养基中成功培养和回收。

公开(公告)号：US06706614B1

公开(公告)日：2004-03-16

申请号：US10145953

申请日：2002-05-15

Applicant: Judy Xilin An ,  Bin Yu

Inventor： Judy Xilin An ,  Bin Yu

IPC: H01L2176

CPC classification number: H01L29/66742 ,  H01L29/78618 ,  H01L29/78684

Abstract: A silicon-on-insulator(SOI) transistor. The SOI transistor having a source and a drain having a body disposed therebetween, the source being implanted with germanium to form an area of silicon-germanium adjacent a source/body junction in a lower portion of the source, the area of silicon-germanium in the source forming a hereto junction along a lower portion of the source/body junction.

Abstract translation: 绝缘体上硅（SOI）晶体管。 具有源极和漏极的SOI晶体管具有设置在其间的主体，源被注入锗以形成邻近源极的下部的源极/主体结的硅 - 锗的区域，硅 - 锗的面积 源沿着源/体结的下部形成本结。

公开(公告)号：US06706571B1

公开(公告)日：2004-03-16

申请号：US10274951

申请日：2002-10-22

Applicant: Bin Yu ,  Judy Xilin An ,  Cyrus E. Tabery ,  Haihong Wang

Inventor： Bin Yu ,  Judy Xilin An ,  Cyrus E. Tabery ,  Haihong Wang

IPC: H01L2100

CPC classification number: H01L29/785 ,  H01L29/4908 ,  H01L29/66795 ,  H01L29/78684

Abstract: A method of forming multiple structures in a semiconductor device includes depositing a film over a conductive layer, etching a trench in a portion of the film and forming adjacent the sidewalls of the trench. The film may then be etched, followed by an of the conductive layer to form the structures.

Abstract translation: 在半导体器件中形成多个结构的方法包括在导电层上沉积膜，蚀刻膜的一部分中的沟槽并且形成在沟槽的侧壁附近。 然后可以对该膜进行蚀刻，然后进行导电层的形成以形成结构。

公开(公告)号：US06686248B1

公开(公告)日：2004-02-03

申请号：US09825658

申请日：2001-04-03

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L21336

CPC classification number: H01L21/28194 ,  H01L21/26586 ,  H01L29/51 ,  H01L29/517 ,  H01L29/6656 ,  H01L29/6659

Abstract: A method for fabricating a semiconductor device, involving: forming a gate stack on a substrate; depositing a material layer on the gate stack; etching the material layer, thereby forming a dielectric capsulate layer on the gate stack; forming a pair of shallow source/drain extensions in a first region of the substrate by implanting a plurality of first dopant ions at a tilt angle with a horizontal offset defined by a thickness of the dielectric capsulate layer; and forming at least one spacer on the dielectric capsulate layer; forming deep source/drain contact junctions in a second region of the substrate by vertically implanting a plurality of second dopant ions below the first region with no tilt and with a horizontal offset defined by a thickness of the at least one spacer.

Abstract translation: 一种制造半导体器件的方法，包括：在衬底上形成栅叠层; 在栅极堆叠上沉积材料层; 蚀刻材料层，从而在栅叠层上形成电介质封装层; 通过以与介电封装层的厚度限定的水平偏移的倾斜角度注入多个第一掺杂剂离子，在衬底的第一区域中形成一对浅源极/漏极延伸部分; 以及在介电封装层上形成至少一个间隔物; 通过在第一区域的下方垂直地注入多个第二掺杂剂离子并且没有由至少一个间隔物的厚度限定的水平偏移，在衬底的第二区域中形成深源/漏接触结。

公开(公告)号：US06642122B1

公开(公告)日：2003-11-04

申请号：US10254850

申请日：2002-09-26

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L21336

CPC classification number: H01L29/66492 ,  H01L21/26506 ,  H01L21/26586 ,  H01L21/268 ,  H01L21/28518 ,  H01L29/1083 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/7833

Abstract: Short-channel effects are controlled by forming abrupt, graded halo profiles. Embodiments include sequentially forming deep source/drain regions, ion implanting to form first deep amorphized regions, ion implanting an impurity into the first deep amorphized regions to form first deep halo implants, laser thermal annealing to recrystallize the first deep amorphized regions and activate the deep halo regions, ion implanting to form second shallow amorphized regions within the deep halo regions, ion implanting an impurity into the second shallow amorphous regions to form second shallow halo implants and laser thermal annealing to recrystallize the second shallow amorphous regions and to activate the shallow halo regions. Embodiments further include forming shallow source/drain extensions within the shallow halo implants and laser thermal annealing to activate the shallow source/drain extensions.

Abstract translation: 短通道效应通过形成突变的渐变晕轮廓来控制。 实施例包括顺序形成深源极/漏极区域，离子注入以形成第一深非晶化区域，将杂质离子注入到第一深非晶化区域中以形成第一深光晕植入物，激光热退火以使第一深非晶化区域再结晶并激活深 卤素区域，离子注入以在深晕区域内形成第二浅非晶化区域，离子将杂质注入第二浅非晶区域以形成第二浅光晕植入物和激光热退火以使第二浅无定形区域再结晶并激活浅光晕 地区。 实施例还包括在浅光晕植入物内形成浅源极/漏极延伸部分以及激光热退火以激活浅源极/漏极延伸部分。

公开(公告)号：US06611029B1

公开(公告)日：2003-08-26

申请号：US10290158

申请日：2002-11-08

Applicant: Shibly S. Ahmed ,  Haihong Wang ,  Bin Yu

Inventor： Shibly S. Ahmed ,  Haihong Wang ,  Bin Yu

IPC: H01L2976

CPC classification number: H01L29/785 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66795

Abstract: A semiconductor device may include a substrate and an insulating layer formed on the subtrate. A fin may be formed on the insulating layer and may include a number of side surfaces and a top surface. A first gate may be formed on the insulating layer proximate to one of the number of side surfaces of the fin. A second gate and may be formed on the insulating layer separate from the first gate and proximate to another one of number of side surfaces of the fin.

Abstract translation: 半导体器件可以包括基板和形成在该副墨滴上的绝缘层。 鳍可以形成在绝缘层上，并且可以包括多个侧表面和顶表面。 第一栅极可以形成在靠近鳍片的多个侧表面中的一个的绝缘层上。 第二栅极，并且可以形成在与第一栅极分离并且靠近鳍片的多个侧表面中的另一个的绝缘层上。

公开(公告)号：US06531368B1

公开(公告)日：2003-03-11

申请号：US09825750

申请日：2001-04-03

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L21336

CPC classification number: H01L21/28194 ,  H01L21/268 ,  H01L21/2807 ,  H01L21/28202 ,  H01L21/28229 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/665 ,  H01L29/66583

Abstract: A method of fabricating a semiconductor device, having a locally-formed metal oxide high-k gate insulator, involving: nitriding a substrate to form a thin silicon nitride layer; depositing a thin metal film on the thin silicon nitride layer; forming a localized metal oxide layer from the thin metal film, wherein the a thick nitride layer is deposited on the thin metal film, the thick nitride layer is patterned, the at least one exposed thin metal film portion is locally oxidized, by heating, wherein the oxidizing is performed by local laser irradiation; forming a gate stack having the localized metal oxide layer and a gate electrode, wherein the a thick gate material is deposited in the electrode cavity and on the localized metal oxide layer; the thick gate material is polished, thereby forming the gate electrode; and the thick nitride layer along with the at least one covered thin metal film portion are removed, thereby forming the gate stack; and completing fabrication of the device, and a device thereby formed.

Abstract translation: 一种制造具有局部形成的金属氧化物高k栅极绝缘体的半导体器件的方法，包括：氮化氮化硅层，形成薄的氮化硅层; 在薄氮化硅层上沉积薄金属薄膜; 从所述薄金属膜形成局部金属氧化物层，其中所述厚氮化物层沉积在所述薄金属膜上，所述厚氮化物层被图案化，所述至少一个暴露的金属薄膜部分通过加热而局部氧化，其中 通过局部激光照射进行氧化; 形成具有局部金属氧化物层和栅电极的栅极堆叠，其中厚栅极材料沉积在电极腔和局部金属氧化物层上; 对厚栅极材料进行抛光，从而形成栅电极; 并且去除厚氮化物层与至少一个覆盖的薄金属膜部分，从而形成栅极堆叠; 并完成该装置的制造以及由此形成的装置。

公开(公告)号：US06524920B1

公开(公告)日：2003-02-25

申请号：US09779988

申请日：2001-02-09

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L21336

CPC classification number: H01L29/517 ,  H01L29/41783 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659

Abstract: A method of manufacturing an integrated circuit utilizes solid phase epitaxy to form an elevated source region and an elevated drain region. The method includes providing an amorphous semiconductor material and crystallizing the amorphous semiconductor material without damaging a high-k gate dielectric layer. The gate structure includes L-shaped liners. The semiconductor material can be silicided. A shallow source drain implant can also be provided.

Abstract translation: 集成电路的制造方法利用固相外延形成升高的源极区域和升高的漏极区域。 该方法包括提供非晶半导体材料并使非晶半导体材料结晶而不损坏高k栅介质层。 门结构包括L形衬垫。 半导体材料可以被硅化。 还可以提供浅源极漏极植入物。

公开(公告)号：US06507078B1

公开(公告)日：2003-01-14

申请号：US10131858

申请日：2002-04-25

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L2976

CPC classification number: H01L29/66545 ,  H01L21/28052 ,  H01L21/28114 ,  H01L29/42376 ,  H01L29/4933

Abstract: A MOSFET has a drain region, a source region, and a channel region, and the MOSFET initially has a gate comprised of a capping layer on a polysilicon structure disposed on a gate dielectric over the channel region. A drain silicide and a source silicide having a first silicide thickness are formed in the drain region and the source region, respectively. A dielectric layer is deposited over the drain region, the source region, and the gate. The dielectric layer is polished until the capping layer of the gate is exposed such that the capping layer and the first dielectric layer are substantially level. The capping layer on the polysilicon structure of the gate is etched away such that the top of the polysilicon structure is exposed. A top portion of the first dielectric layer is etched away until sidewalls at a top portion of the polysilicon structure are exposed. A polysilicon spacer is formed at the exposed sidewalls at the top portion of the polysilicon structure. A silicidation metal is deposited on the top of the polysilicon structure that is exposed and on the polysilicon spacer. A silicidation anneal is performed with the silicidation metal and the polysilicon structure that is exposed and the polysilicon spacer to form a gate silicide having a second silicide thickness on top of the polysilicon structure of the gate. Because the gate silicide is formed with the added polysilicon spacer at the exposed sidewalls of the polysilicon structure, the gate silicide has a width that is larger than a width of the polysilicon structure of the gate. In addition, the gate silicide is formed in a separate step from the step for forming the drain silicide and the source silicide such that the gate silicide may have a larger thickness and be comprised of different metal silicide material from that of the drain silicide and the source silicide.

公开(公告)号：US06492670B1

公开(公告)日：2002-12-10

申请号：US09821258

申请日：2001-03-29

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L2980

CPC classification number: H01L29/66492 ,  H01L29/665

Abstract: A method of fabricating an integrated circuit with locally confined deep pocket regions utilizes a dummy or sacrificial gate spacer. Dopants are provided through the openings associated with sacrificial spacers to form the pocket regions. The dopants are provided after silicidation. The openings can be filled with spacers. The process can be utilized for P-channel or N-channel metal oxide field semiconductor effect transistors (MOSFETS).

Abstract translation: 制造具有局部密封深口袋区域的集成电路的方法利用虚拟或牺牲栅极间隔物。 通过与牺牲间隔物相关联的开口提供掺杂剂以形成袋区域。 在硅化后提供掺杂剂。 开口可以填充间隔件。 该过程可用于P沟道或N沟道金属氧化物半导体效应晶体管（MOSFET）。