公开(公告)号：US20150236106A1

公开(公告)日：2015-08-20

申请号：US14184830

申请日：2014-02-20

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Mark A. Zaleski ,  Andy Chih-Hung Wei ,  Jason E. Stephens ,  Tuhin Guha Neogi ,  Guillaume Bouche

IPC: H01L29/417 ,  H01L29/78 ,  H01L27/088 ,  H01L29/66 ,  H01L29/51

CPC classification number: H01L29/41758 ,  H01L21/8234 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823871 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/165 ,  H01L29/41791 ,  H01L29/518 ,  H01L29/66348 ,  H01L29/66484 ,  H01L29/66545 ,  H01L29/66613 ,  H01L29/66621 ,  H01L29/66727 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: Embodiments of the present invention provide improved methods of contact formation. A self aligned contact scheme with reduced lithography requirements is disclosed. This reduces the risk of shorts between source/drains and gates, while providing improved circuit density. Cavities are formed adjacent to the gates, and a fill metal is deposited in the cavities to form contact strips. A patterning mask is then used to form smaller contacts by performing a partial metal recess of the contact strips.

Abstract translation: 本发明的实施例提供改进的接触形成方法。 公开了一种具有降低光刻要求的自对准接触方案。 这降低了源/漏极和栅极之间短路的风险，同时提供了改善的电路密度。 形成邻近门的腔，并且填充金属沉积在空腔中以形成接触条。 然后通过执行接触片的部分金属凹部来使用图案化掩模来形成更小的触点。

公开(公告)号：US20150214228A1

公开(公告)日：2015-07-30

申请号：US14167778

申请日：2014-01-29

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Shao Ming Koh ,  Guillaume Bouche ,  Jeremy A. Wahl ,  Andy C. Wei

IPC: H01L27/092 ,  H01L29/45 ,  H01L29/161 ,  H01L21/02 ,  H01L29/16 ,  H01L29/167 ,  H01L21/311 ,  H01L21/8238

CPC classification number: H01L29/7839 ,  H01L21/02532 ,  H01L21/31111 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823871 ,  H01L21/845 ,  H01L27/0922 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/161 ,  H01L29/167 ,  H01L29/24 ,  H01L29/41791 ,  H01L29/45 ,  H01L29/456 ,  H01L29/665 ,  H01L29/7848

Abstract: Integrated circuits having silicide contacts with reduced contact resistance and methods for fabricating integrated circuits having silicide contacts with reduced contact resistance are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a semiconductor substrate having selected source/drain regions and non-selected source/drain regions. The method forms a contact resistance modulation material over the selected source/drain regions. Further, the method forms a metal layer over the selected and non-selected source/drain regions. The method includes annealing the metal layer to form silicide contacts on the selected and non-selected source/drain regions.

Abstract translation: 提供了具有降低的接触电阻的硅化物接触的集成电路和用于制造具有降低的接触电阻的具有硅化物接触的集成电路的方法。 在一个实施例中，一种用于制造集成电路的方法包括提供具有选定的源极/漏极区域和未选择的源极/漏极区域的半导体衬底。 该方法在选定的源极/漏极区域上形成接触电阻调制材料。 此外，该方法在所选择的和非选择的源/漏区上形成金属层。 该方法包括退火金属层以在所选择的和非选择的源/漏区上形成硅化物接触。