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    Ternary content addressable memories having a bit cell with memristors and serially connected match-line transistors
    141.
    发明授权
    Ternary content addressable memories having a bit cell with memristors and serially connected match-line transistors 有权

    公开(公告)号：US09934857B2

    公开(公告)日：2018-04-03

    申请号：US15228559

    申请日：2016-08-04

    Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

    Inventor： Le Zheng ,  Brent Buchanan ,  John Paul Strachan

    IPC: G11C15/00 ,  G11C15/04

    CPC classification number: G11C15/046

    Abstract: An example ternary content addressable memory. A bit cell of the memory may include a first memristor that has a first terminal that is connected to a first data line and a second terminal that is selectively connected to a second data line via a first switching transistor. The bit cell may also include a second memristor that has a first terminal that is connected to a third data line and a second terminal that is selectively connected to a fourth data line via a second switching transistor. The bit cell may also include a first match-line transistor and a second match-line transistor that are connected in series between a first rail and a match line, with a gate of the first match-line transistor being connected to the second terminal of the first memristor, and a gate of the second match-line transistor being connected to the second terminal of the second memristor.

    NONVOLATILE MEMORY CROSS-BAR ARRAY
    142.
    发明申请
    NONVOLATILE MEMORY CROSS-BAR ARRAY 审中-公开

    公开(公告)号：US20170358352A1

    公开(公告)日：2017-12-14

    申请号：US15535765

    申请日：2014-12-15

    Applicant: Hewlett Packard Enterprise Development LP

    Inventor： Ning Ge ,  Jianhua Yang ,  John Paul Strachan ,  Miao Hu

    IPC: G11C13/00

    CPC classification number: G11C13/0069 ,  G06G7/16 ,  G11C13/0007 ,  G11C13/004 ,  G11C2213/79

    Abstract: Provided in one example is a nonvolatile memory cross-bar array. The array includes: a number of junctions formed by a number of row lines intersecting a number of column lines; a first set of controls at a first set of the junctions coupling between a first set of the row lines and a first set of the column lines; a second set of controls at a second set of the junctions coupling between a second set of the row lines and a second set of the column lines; and a current collection line to collect currents from the controls of the first set and the second set through their respective column lines and output a result current corresponding to a sum of a first dot product and a second dot product.

    Content addressable memory with banks
    146.
    发明授权
    Content addressable memory with banks 有权

    公开(公告)号：US09691483B1

    公开(公告)日：2017-06-27

    申请号：US15270087

    申请日：2016-09-20

    Applicant: Hewlett Packard Enterprise Development LP

    Inventor： Brent Buchanan ,  John Paul Strachan ,  Le Zheng

    IPC: G11C15/00 ,  G06F3/06

    CPC classification number: G11C15/00

    Abstract: In one aspect, techniques for providing a banked content addressable memory (CAM) with counters are provided. A dictionary word may be divided into a plurality of banks. A counter may be associated with each bank of the plurality of banks. The counter may count the number of times a segment of an input word aligned with the bank does not match. A scheduler may schedule comparison of banks with higher probability of not matching before banks with lower probability of not matching. The probability of not matching may be based on the counters.

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