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公开(公告)号：US20200381030A1
公开(公告)日：2020-12-03
申请号：US16998346
申请日：2020-08-20
Applicant: Micron Technology, Inc.
Inventor： Andrea Redaelli
Abstract: Methods, systems, and devices for a decoder are described. The memory device may include a substrate, an array of memory cells coupled with the substrate, and a decoder coupled with the substrate. The decoder may include a doped material that may extend between a first conductive line and an access line of the array of memory cells in a first direction (e.g., away from a surface of the substrate) and the doped material may be configured to selectively couple the first conductive line of the decoder with the access line of the array of memory cells. The access line may be coupled with two decoders, in some cases.
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公开(公告)号：US20200303462A1
公开(公告)日：2020-09-24
申请号：US16892459
申请日：2020-06-04
Applicant: Micron Technology, Inc.
Inventor： Fabio Pellizzer , Andrea Redaelli , Agostino Pirovano , Innocenzo Tortorelli
Abstract: The present disclosure includes memory cells having resistors, and methods of forming the same. An example method includes forming a first conductive line, forming a second conductive line, and forming a memory element between the first conductive line and the second conductive line. Forming the memory element can include forming one or more memory materials, and forming a resistor in series with the one or more memory materials. The resistor can be configured to reduce a capacitive discharge through the memory element during a state transition of the memory element.
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公开(公告)号：US10777245B2
公开(公告)日：2020-09-15
申请号：US16253485
申请日：2019-01-22
Applicant: Micron Technology, Inc.
Inventor： Andrea Redaelli
Abstract: Methods, systems, and devices for a decoder are described. The memory device may include a substrate, an array of memory cells coupled with the substrate, and a decoder coupled with the substrate. The decoder may include a doped material that may extend between a first conductive line and an access line of the array of memory cells in a first direction (e.g., away from a surface of the substrate) and the doped material may be configured to selectively couple the first conductive line of the decoder with the access line of the array of memory cells. The access line may be coupled with two decoders, in some cases.
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公开(公告)号：US10693065B2
公开(公告)日：2020-06-23
申请号：US15893100
申请日：2018-02-09
Applicant: Micron Technology, Inc.
Inventor： Andrea Redaelli , Anna Maria Conti , Agostino Pirovano
Abstract: Methods, systems, and devices for a tapered cell profile and fabrication are described. A memory storage component may contain multiple chalcogenide materials and may include a tapered profile. For example, a first chalcogenide material may be coupled with a second chalcogenide material. Each of the chalcogenide materials may be further coupled with a conductive material (e.g., an electrode). Through an etching process, the chalcogenide materials may tapered (e.g., step tapered). A pulse may be applied to the tapered chalcogenide materials resulting in a memory storage component that includes a mixture of the chalcogenide materials.
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公开(公告)号：US20190252605A1
公开(公告)日：2019-08-15
申请号：US15893100
申请日：2018-02-09
Applicant: Micron Technology, Inc.
Inventor： Andrea Redaelli , Anna Maria Conti , Agostino Pirovano
Abstract: Methods, systems, and devices for a tapered cell profile and fabrication are described. A memory storage component may contain multiple chalcogenide materials and may include a tapered profile. For example, a first chalcogenide material may be coupled with a second chalcogenide material. Each of the chalcogenide materials may be further coupled with a conductive material (e.g., an electrode). Through an etching process, the chalcogenide materials may tapered (e.g., step tapered). A pulse may be applied to the tapered chalcogenide materials resulting in a memory storage component that includes a mixture of the chalcogenide materials.
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Patent Agency Ranking
公开(公告)号：US10381075B2
公开(公告)日：2019-08-13
申请号：US15842504
申请日：2017-12-14
Applicant: Micron Technology, Inc.
Inventor： Innocenzo Totorelli , Andrea Redaelli , Agostino Pirovano , Fabio Pellizzer , Mario Allegra , Paolo Fantini
Abstract: Methods, systems, and devices related to techniques to access a self-selecting memory device are described. A self-selecting memory cell may store one or more bits of data represented by different threshold voltages of the self-selecting memory cell. A programming pulse may be varied to establish the different threshold voltages by modifying one or more time durations during which a fixed level of voltage or current is maintained across the self-selecting memory cell. The self-selecting memory cell may include a chalcogenide alloy. A non-uniform distribution of an element in the chalcogenide alloy may determine a particular threshold voltage of the self-selecting memory cell. The shape of the programming pulse may be configured to modify a distribution of the element in the chalcogenide alloy based on a desired logic state of the self-selecting memory cell.
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公开(公告)号：US10305036B2
公开(公告)日：2019-05-28
申请号：US15994815
申请日：2018-05-31
Applicant: Micron Technology, Inc.
Inventor： Mattia Boniardi , Andrea Redaelli
Abstract: A thermally optimized phase change memory cell includes a phase change material element disposed between first and second electrodes. The second electrode includes a thermally insulating region having a first thermal resistivity over the first electrode and a metallic contact region interposed between the phase change material element and the thermally insulating region, where the metallic contact layer has a second thermal resistivity lower than the first thermal resistivity.
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公开(公告)号：US20190123105A1
公开(公告)日：2019-04-25
申请号：US16216100
申请日：2018-12-11
Applicant: Micron Technology, Inc.
Inventor： Fabio Pellizzer , Andrea Redaelli , Agostino Pirovano , Innocenzo Tortorelli
Abstract: The present disclosure includes memory cells having resistors, and methods of forming the same. An example method includes forming a first conductive line, forming a second conductive line, and forming a memory element between the first conductive line and the second conductive line. Forming the memory element can include forming one or more memory materials, and forming a resistor in series with the one or more memory materials. The resistor can be configured to reduce a capacitive discharge through the memory element during a state transition of the memory element.
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公开(公告)号：US20190081104A1
公开(公告)日：2019-03-14
申请号：US16185729
申请日：2018-11-09
Applicant: Micron Technology, Inc.
Inventor： Ugo Russo , Andrea Redaelli , Giorgio Servalli
Abstract: Phase change memory apparatuses include memory cells including phase change material, bit lines electrically coupled to aligned groups of at least some of the memory cells, and heating elements electrically coupled to the phase change material of the memory cells. The heating elements include vertical portions extending in a bit line direction. Additional phase change memory apparatuses include dummy columns positioned between memory columns and base contact columns. The dummy columns include phase change memory cells and lack heating elements coupled to the phase change memory cells thereof. Additional phase change memory apparatuses include heating elements operably coupled to phase change memory cells. An interfacial area between the heating elements and the phase change memory cells has a length that is independent of a bit line width. Methods relate to forming such phase change memory apparatuses.
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公开(公告)号：US20190067371A1
公开(公告)日：2019-02-28
申请号：US15689155
申请日：2017-08-29
Applicant: Micron Technology, Inc.
Inventor： Agostino Pirovano , Andrea Redaelli , Fabio Pellizzer , Innocenzo Tortorelli
IPC: H01L27/24 , H01L45/00 , H01L27/115
Abstract: In an example, a memory array may include a plurality of first dielectric materials and a plurality of stacks, where each respective first dielectric material and each respective stack alternate, and where each respective stack comprises a first conductive material and a storage material. A second conductive material may pass through the plurality of first dielectric materials and the plurality of stacks. Each respective stack may further include a second dielectric material between the first conductive material and the second conductive material.
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