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    Sample Adaptive Offset (SAO) Parameter Signaling
    141.
    发明申请
    Sample Adaptive Offset (SAO) Parameter Signaling 有权
    采样自适应偏移（SAO）参数信号

    公开(公告)号：US20130223542A1

    公开(公告)日：2013-08-29

    申请号：US13775064

    申请日：2013-02-22

    Applicant: Texas Instruments Incorporated

    Inventor： Woo-Shik Kim ,  Do-Kyoung Kwon ,  Minhua Zhou

    IPC: H04N7/26

    CPC classification number: H04N19/86 ,  H04N19/117 ,  H04N19/186 ,  H04N19/463 ,  H04N19/70 ,  H04N19/80 ,  H04N19/82 ,  H04N19/91

    Abstract: Techniques for signaling of sample adaptive offset (SAO) information that may reduce the coding rate for signaling such information in the compressed bit stream are provided. More specifically, techniques are provided that allow SAO information common to two or more of the color components to be signaled using one or more syntax elements (flags or indicators) representative of the common information. These techniques reduce the need to signal SAO information separately for each color component.

    Abstract translation: 提供了可以降低用于在压缩比​​特流中发送信令的编码率的采样自适应偏移（SAO）信息的信令技术。 更具体地，提供了允许使用表示公共信息的一个或多个语法元素（标志或指示符）来向两个或多个颜色分量公共的SAO信息进行信令的技术。 这些技术减少了为每个颜色分量分别发出信号SAO信息的需要。

    Sub-Pictures for Pixel Rate Balancing on Multi-Core Platforms
    142.
    发明申请
    Sub-Pictures for Pixel Rate Balancing on Multi-Core Platforms 审中-公开
    多核平台像素率平衡子图

    公开(公告)号：US20130202051A1

    公开(公告)日：2013-08-08

    申请号：US13757791

    申请日：2013-02-02

    Applicant: Texas Instruments Incorporated

    Inventor： Minhua Zhou

    IPC: H04N7/26

    CPC classification number: H04N19/436

    Abstract: A method for decoding a compressed video bit stream in a video decoder to recover a video sequence, the video decoder including a plurality of decoder processing cores is provided. The method includes determining that a picture is encoded in the compressed bit stream as a pre-determined number of independently encoded sub-pictures, and dispatching a first encoded sub-picture of the pre-determined number of sub-pictures to a first decoder processing core of the plurality of decoder processing cores and a second encoded sub-picture of the pre-determined number of sub-pictures to a second decoder processing core of the plurality of decoder processing cores, wherein the first encoded sub-picture and the second encoded sub-picture are independently decoded in parallel on the respective first and second decoder processing cores.

    Abstract translation: 一种用于解码视频解码器中的压缩视频比特流以恢复视频序列的方法，提供了包括多个解码器处理核心的视频解码器。 该方法包括：将图像编码在压缩比特流中作为预定数量的独立编码子图像，并将预定数量的子图像的第一编码子图像调度到第一解码器处理 多个解码器处理核心的核心和预定数量的子图像的第二编码子图像到多个解码器处理核心的第二解码器处理核心，其中第一编码子图像和第二编码子图像 子图像在相应的第一和第二解码器处理核上并行独立地解码。

    Scalable prediction type coding
    145.
    发明授权
    Scalable prediction type coding 有权

    公开(公告)号：US12273541B2

    公开(公告)日：2025-04-08

    申请号：US18409147

    申请日：2024-01-10

    Applicant: Texas Instruments Incorporated

    Inventor： Minhua Zhou

    IPC: H04N19/176 ,  H04N19/119 ,  H04N19/13 ,  H04N19/147 ,  H04N19/15 ,  H04N19/174 ,  H04N19/50

    Abstract: A method for encoding a video sequence is provided that includes signaling in the compressed bit stream that a subset of a plurality of partitioning modes is used for inter-prediction of a portion of the video sequence, using only the subset of partitioning modes for prediction of the portion of the video sequence, and entropy encoding partitioning mode syntax elements corresponding to the portion of the video sequence, wherein at least one partitioning mode syntax element is binarized according to a pre-determined binarization corresponding to the subset of partitioning modes, wherein the pre-determined binarization differs from a pre-determined binarization for the least one partitioning mode syntax element that would be used if the plurality of partitioning modes is used for inter-prediction.

    BLOCK-BASED PARALLEL DEBLOCKING FILTER IN VIDEO CODING
    147.
    发明公开
    BLOCK-BASED PARALLEL DEBLOCKING FILTER IN VIDEO CODING 审中-公开

    公开(公告)号：US20240314363A1

    公开(公告)日：2024-09-19

    申请号：US18676745

    申请日：2024-05-29

    Applicant: Texas Instruments Incorporated

    Inventor： Mangesh Devidas Sadafale ,  Minhua Zhou

    IPC: H04N19/86 ,  H04N19/117 ,  H04N19/157 ,  H04N19/176 ,  H04N19/436

    CPC classification number: H04N19/86 ,  H04N19/117 ,  H04N19/157 ,  H04N19/176 ,  H04N19/436

    Abstract: Deblocking filtering is provided in which an 8×8 filtering block covering eight sample vertical and horizontal boundary segments is divided into filtering sub-blocks that can be independently processed. To process the vertical boundary segment, the filtering block is divided into top and bottom 8×4 filtering sub-blocks, each covering a respective top and bottom half of the vertical boundary segment. To process the horizontal boundary segment, the filtering block is divided into left and right 4×8 filtering sub-blocks, each covering a respective left and right half of the horizontal boundary segment. The computation of the deviation d for a boundary segment in a filtering sub-block is performed using only samples from rows or columns in the filtering sub-block. Consequently, the filter on/off decisions and the weak/strong filtering decisions of the deblocking filtering are performed using samples contained within individual filtering blocks, thus allowing full parallel processing of the filtering blocks.

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