公开(公告)号：US10700183B2

公开(公告)日：2020-06-30

申请号：US16226827

申请日：2018-12-20

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kuo-Cheng Ching ,  Kuan-Ting Pan ,  Shi-Ning Ju ,  Chih-Hao Wang

IPC: H01L27/088 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L21/762

Abstract: A method for forming a FinFET device structure includes forming a first fin structure in a core region of a substrate and a second fin structure in an input/output region of the substrate with a fin top layer and a hard mask layer over the fin structures. The method also includes forming a dummy oxide layer across the fin structures. The method also includes forming a dummy gate structure over the dummy oxide layer. The method also includes removing the dummy gate structure over fin structures. The method also includes removing the dummy oxide layer and trimming the fin structures. The method also includes forming first and second oxide layers across the first and second fin structures. The method also includes forming first and second gate structures over the first and second oxide layers across the first and second fin structures.

公开(公告)号：US10672892B2

公开(公告)日：2020-06-02

申请号：US16504829

申请日：2019-07-08

Applicant: Taiwan Semiconductor Manufacturing, Co., Ltd.

Inventor： Kuo-Cheng Ching ,  Chih-Hao Wang ,  Kuan-Lun Cheng

IPC: H01L29/66 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L21/8238 ,  H01L21/02 ,  H01L29/165 ,  H01L29/417 ,  H01L29/161 ,  H01L29/78

Abstract: Semiconductor structures including active fin structures, dummy fin structures, epitaxy layers, a Ge containing oxide layer and methods of manufacture thereof are described. By implementing the Ge containing oxide layer on the surface of the epitaxy layers formed on the source/drain regions of some of the FinFET devices, a self-aligned epitaxy process is enabled. By implementing dummy fin structures and a self-aligned etch, both the epitaxy layers and metal gate structures from adjacent FinFET devices are isolated in a self-aligned manner.

公开(公告)号：US20200098759A1

公开(公告)日：2020-03-26

申请号：US16370258

申请日：2019-03-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Huan-Chieh Su ,  Zhi-Chang Lin ,  Ting-Hung Hsu ,  Jia-Ni Yu ,  Wei-Hao Wu ,  Yu-Ming Lin ,  Chih-Hao Wang

IPC: H01L27/092 ,  H01L29/51 ,  H01L29/78 ,  H01L21/8238 ,  H01L29/66 ,  H01L21/308 ,  H01L21/28

Abstract: A semiconductor device includes a first transistor and a second transistor. The first transistor includes: a first source and a first drain separated by a first distance, a first semiconductor structure disposed between the first source and first drain, a first gate electrode disposed over the first semiconductor structure, and a first dielectric structure disposed over the first gate electrode. The first dielectric structure has a lower portion and an upper portion disposed over the lower portion and wider than the lower portion. The second transistor includes: a second source and a second drain separated by a second distance greater than the first distance, a second semiconductor structure disposed between the second source and second drain, a second gate electrode disposed over the second semiconductor structure, and a second dielectric structure disposed over the second gate electrode. The second dielectric structure and the first dielectric structure have different material compositions.

公开(公告)号：US20200091312A1

公开(公告)日：2020-03-19

申请号：US16686475

申请日：2019-11-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Cheng Ching ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/08

Abstract: A method includes receiving a substrate; forming on the substrate a semiconductor fin; an isolation structure surrounding the semiconductor fin; and first and second dielectric fins above the isolation structure and sandwiching the semiconductor fin; depositing a spacer feature filling spaces between the semiconductor fin and the first and second dielectric fins; performing an etching process to recess the semiconductor fin, resulting in a trench between portions of the spacer feature; and epitaxially growing a semiconductor material in the trench.

公开(公告)号：US20200043919A1

公开(公告)日：2020-02-06

申请号：US16215676

申请日：2018-12-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Cheng Ching ,  Chih-Hao Wang ,  Huan-Chieh Su ,  Mao-Lin Huang ,  Zhi-Chang Lin

IPC: H01L27/088 ,  H01L29/78 ,  H01L29/66 ,  H01L29/423 ,  H01L21/8234

Abstract: Provided are FinFET devices and methods of forming the same. A FinFET device includes a substrate, a metal gate strip, gate spacers and a dielectric helmet. The substrate has fins. The metal gate strip is disposed across the fins and has a reversed T-shaped portion between two adjacent fins. The gate spacers are disposed on opposing sidewalls of the metal gate strip. A dielectric helmet is disposed over the metal gate strip.

公开(公告)号：US20200006547A1

公开(公告)日：2020-01-02

申请号：US16284871

申请日：2019-02-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chi-Hsing Hsu ,  Ching-Wei Tsai ,  Kuan-Lun Cheng ,  Chih-Hao Wang ,  Sai-Hooi Yeong

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L27/088

Abstract: A semiconductor device includes a substrate. The semiconductor device includes a dielectric layer disposed over a portion of the substrate. The semiconductor device includes a diffusion blocking layer disposed over the dielectric layer. The diffusion blocking layer and the dielectric layer have different material compositions. The semiconductor device includes a ferroelectric layer disposed over the diffusion blocking layer.

公开(公告)号：US10516051B2

公开(公告)日：2019-12-24

申请号：US15235233

申请日：2016-08-12

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kuo-Cheng Ching ,  Kuan-Ting Pan ,  Ching-Wei Tsai ,  Ying-Keung Leung ,  Chih-Hao Wang ,  Carlos H. Diaz

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/51

Abstract: The present disclosure provides a fin-like field effect transistor (FinFET) device and a method of fabrication thereof. The method includes forming a fin on a substrate and forming a gate structure wrapping the fin. A pair of spacers is formed adjacent to the gate structure and the gate structure is removed. Afterwards, a pair of oxide layers is deposited adjacent to the pair of spacers. A pair of gate dielectric layers is deposited next to the pair of oxide layers. Finally, a metal gate is formed between the pair of gate dielectric layers.

公开(公告)号：US10510860B2

公开(公告)日：2019-12-17

申请号：US15801171

申请日：2017-11-01

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chun-Hsiung Lin ,  Chia-Hao Chang ,  Chih-Hao Wang ,  Wai-Yi Lien ,  Chih-Chao Chou ,  Pei-Yu Wang

IPC: H01L29/49 ,  H01L29/66 ,  H01L29/78 ,  H01L21/764 ,  H01L21/28 ,  H01L21/8238 ,  H01L27/092

Abstract: In a method for manufacturing a semiconductor device, a gate structure is formed over a channel layer and an isolation insulating layer. A first sidewall spacer layer is formed on a side surface of the gate structure. A sacrificial layer is formed so that an upper portion of the gate structure with the first sidewall spacer layer is exposed from the sacrificial layer and a bottom portion of the gate structure with the first sidewall spacer layer is embedded in the first sacrificial layer. A space is formed between the bottom portion of the gate structure and the sacrificial layer by removing at least part of the first sidewall spacer layer. After the first sidewall spacer layer is removed, an air gap is formed between the bottom portion of the gate structure and the sacrificial layer by forming a second sidewall spacer layer over the gate structure.

公开(公告)号：US10361126B2

公开(公告)日：2019-07-23

申请号：US15987009

申请日：2018-05-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Cheng Ching ,  Shi Ning Ju ,  Chih-Hao Wang ,  Ying-Keung Leung ,  Carlos H. Diaz

IPC: H01L21/02 ,  H01L29/66 ,  H01L29/78 ,  H01L21/762 ,  H01L21/8234 ,  H01L21/8238

Abstract: A semiconductor layer is etched into a plurality of fin structures. A first nitridation process is performed to side surfaces of the fin structures. The first nitridation process forms a first oxynitride layer at the side surfaces of the fin structures. A liner oxide layer is formed on the first oxynitride layer. An isolation structure is formed around the fin structures after the forming of the liner oxide layer.

公开(公告)号：US20190164840A1

公开(公告)日：2019-05-30

申请号：US16246209

申请日：2019-01-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Cheng Ching ,  Chih-Hao Wang ,  Kuan-Ting Pan

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/08 ,  H01L29/66 ,  H01L29/423 ,  H01L29/78

Abstract: A method of forming first and second fin field effect transistors (finFETs) on a substrate includes forming first and second fin structures of the first and second finFETs, respectively, on the substrate and forming first and second oxide regions having first and second thicknesses on top surfaces of the first and second fin structures, respectively. The method further includes forming third and fourth oxide regions having third and fourth thicknesses on sidewalls on the first and second fin structures, respectively. The first and second thicknesses are greater than the third and fourth thicknesses, respectively. The method further includes forming a first polysilicon structure on the first and third oxide regions and forming a second polysilicon structure on the second and fourth oxide regions. The method also includes forming first and second source/drain regions on first and second recessed portions of the first and second fin structures, respectively and replacing the first and second polysilicon structures with first and second gate structures, respectively