公开(公告)号：US11056445B2

公开(公告)日：2021-07-06

申请号：US16731517

申请日：2019-12-31

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hsiao-Wen Lee ,  Hsien-Wen Liu ,  Shin-Puu Jeng

IPC: H01L23/495 ,  H01L23/00 ,  H01L23/538 ,  H01L23/31 ,  H01L21/304 ,  H01L21/56 ,  H01L21/683 ,  H01L21/78 ,  H01L21/02 ,  H01L21/48 ,  H01L23/498

Abstract: Package structures are provided. A package structure includes an adhesive layer and a semiconductor substrate over the adhesive layer. The package structure also includes a connector over the semiconductor substrate. The package structure further includes a first buffer layer surrounding the connector. In addition, the package structure includes an encapsulation layer surrounding the first buffer layer. The first buffer layer is sandwiched between the encapsulation layer and the semiconductor substrate, and a sidewall of the encapsulation layer is in direct contact with a sidewall of the first buffer layer and a sidewall of the adhesive layer. The package structure also includes a redistribution layer over the first buffer layer and the encapsulation layer.

公开(公告)号：US20210193637A1

公开(公告)日：2021-06-24

申请号：US17022791

申请日：2020-09-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shin-Puu Jeng ,  Shuo-Mao Chen ,  Feng-Cheng Hsu

IPC: H01L25/16 ,  H01L23/538 ,  H01L23/31 ,  H01L25/00 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L25/065

Abstract: A method includes bonding a first package component and a second package component to an interposer. The first package component includes a core device die, and the second package component includes a memory die. An Independent Passive Device (IPD) die is bonded directly to the interposer. The IPD die is electrically connected to the first package component through a first conductive path in the interposer. A package substrate is bonded to the interposer die. The package substrate is on an opposing side of the interposer than the first package component and the second package component.

公开(公告)号：US10985100B2

公开(公告)日：2021-04-20

申请号：US16717901

申请日：2019-12-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shin-Puu Jeng ,  Po-Hao Tsai ,  Po-Yao Chuang ,  Feng-Cheng Hsu ,  Shuo-Mao Chen ,  Techi Wong

IPC: H01L23/498 ,  H01L25/10 ,  H01L21/52 ,  H01L21/56 ,  H01L23/00 ,  H01L21/48 ,  H01L23/053 ,  H01L21/683 ,  H01L25/00 ,  H01L23/31

Abstract: A chip package is provided. The chip package includes a redistribution structure including an insulating layer and a wiring layer. The wiring layer is in the insulating layer. The chip package includes a chip over the redistribution structure and electrically connected to the wiring layer. The chip package includes an interposer substrate over the redistribution structure and the chip, wherein a portion of the chip is in the interposer substrate. The chip package includes a conductive structure between the interposer substrate and the redistribution structure and electrically connected to the wiring layer. The conductive structure includes a conductive bump or a conductive pillar. The chip package includes a molding layer surrounding the interposer substrate and the conductive structure. The molding layer is partially between the interposer substrate and the redistribution structure and partially between the interposer substrate and the chip.

公开(公告)号：US20210057387A1

公开(公告)日：2021-02-25

申请号：US17073953

申请日：2020-10-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Shin-Puu Jeng ,  Der-Chyang Yeh ,  Hsien-Wei Chen ,  Cheng-Chieh Hsieh ,  Ming-Yen Chiu

IPC: H01L25/065 ,  H01L23/498 ,  H01L21/56 ,  H01L25/10 ,  H01L23/367 ,  H01L23/31 ,  H01L21/48

Abstract: A first package is bonded to a first substrate with first external connections and second external connections. The second external connections are formed using materials that are different than the first external connections in order to provide a thermal pathway from the first package. In a particular embodiment the first external connections are solder balls and the second external connections are copper blocks.

公开(公告)号：US10910267B2

公开(公告)日：2021-02-02

申请号：US16908348

申请日：2020-06-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin Chang ,  Fang Wen Tsai ,  Jing-Cheng Lin ,  Wen-Chih Chiou ,  Shin-Puu Jeng

IPC: H01L21/768 ,  H01L23/544 ,  H01L23/00 ,  H01L21/683 ,  H01L23/48 ,  H01L23/498

Abstract: A device includes a substrate, and an alignment mark including a conductive through-substrate via (TSV) penetrating through the substrate.

公开(公告)号：US10854563B2

公开(公告)日：2020-12-01

申请号：US16880928

申请日：2020-05-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Kuei Hsu ,  Ming-Chih Yew ,  Po-Hao Tsai ,  Po-Yao Lin ,  Shin-Puu Jeng

IPC: H01L23/00 ,  H01L23/31 ,  H01L21/56 ,  H01L21/768

Abstract: A redistribution structure includes a first dielectric layer, a pad pattern, and a second dielectric layer. The pad pattern is disposed on the first dielectric layer and includes a pad portion and a peripheral portion. The pad portion is embedded in the first dielectric layer, wherein a lower surface of the pad portion is substantially coplanar with a lower surface of the first dielectric layer. The peripheral portion surrounds the pad portion. The second dielectric layer is disposed on the pad pattern and includes a plurality of extending portions extending through the peripheral portion.

公开(公告)号：US10790164B1

公开(公告)日：2020-09-29

申请号：US16439944

申请日：2019-06-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen-Yi Lin ,  Che-Chia Yang ,  Kuang-Chun Lee ,  Yu-Sheng Lin ,  Po-Yao Lin ,  Shin-Puu Jeng

IPC: H01L23/373 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L23/522 ,  H01L25/065 ,  H01L23/29

Abstract: A method for forming a package structure is provided. The method includes forming a first die over a first substrate, and injecting a molding compound material from a first side of the first die to a second side of the first die. The molding compound material includes a plurality of first fillers, each of the first fillers has a length along a longitudinal axis and a width along a transverse direction, and the length is greater than the width. The method further includes heating the molding compound material to form a package layer over the first die, and the first fillers are substantially parallel to each other.

公开(公告)号：US10784220B2

公开(公告)日：2020-09-22

申请号：US15800035

申请日：2017-10-31

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Shin-Puu Jeng ,  Shuo-Mao Chen ,  Feng-Cheng Hsu

IPC: H01L23/02 ,  H01L23/34 ,  H01L23/48 ,  H01L23/28 ,  H01L21/00 ,  H01L21/44 ,  H01L23/00 ,  H01L23/31 ,  H01L21/683 ,  H01L25/065 ,  H01L25/00 ,  H01L25/10 ,  H01L23/498 ,  H01L21/56 ,  H01L23/538

Abstract: A package structure includes a first dielectric layer, a first semiconductor device, a first redistribution line, a second dielectric layer, a second semiconductor device, a second redistribution line, a first conductive feature, and a first molding material. The first semiconductor device is over the first dielectric layer. The first redistribution line is in the first dielectric layer and is electrically connected to the first semiconductor device. The second dielectric layer is over the first semiconductor device. The second semiconductor device is over the second dielectric layer. The second redistribution line is in the second dielectric layer and is electrically connected to the second semiconductor device. The first conductive feature electrically connects the first redistribution line and the second redistribution line. The first molding material molds the first semiconductor device and the first conductive feature.

公开(公告)号：US20200286843A1

公开(公告)日：2020-09-10

申请号：US16880928

申请日：2020-05-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Kuei Hsu ,  Ming-Chih Yew ,  Po-Hao Tsai ,  Po-Yao Lin ,  Shin-Puu Jeng

IPC: H01L23/00 ,  H01L23/31 ,  H01L21/56 ,  H01L21/768

Abstract: A redistribution structure includes a first dielectric layer, a pad pattern, and a second dielectric layer. The pad pattern is disposed on the first dielectric layer and includes a pad portion and a peripheral portion. The pad portion is embedded in the first dielectric layer, wherein a lower surface of the pad portion is substantially coplanar with a lower surface of the first dielectric layer. The peripheral portion surrounds the pad portion. The second dielectric layer is disposed on the pad pattern and includes a plurality of extending portions extending through the peripheral portion.

公开(公告)号：US10692813B2

公开(公告)日：2020-06-23

申请号：US15398724

申请日：2017-01-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Feng-Cheng Hsu ,  Shin-Puu Jeng

IPC: H01L23/528 ,  H01L23/498 ,  H01L23/00 ,  H01L21/683 ,  H01L21/48

Abstract: A semiconductor device including an integrated circuit, a dielectric layer, a plurality of connecting terminals and at least one dummy conductor is provided. The integrated circuit has a plurality of connecting pads, and the dielectric layer is disposed thereon and partially exposes the plurality of the connecting pads by a plurality of openings defined therein. The plurality of the connecting terminals is disposed on the plurality of the connecting pads exposed by the plurality of the openings. The at least one dummy conductor is disposed on the dielectric layer and electrically isolated from the integrated circuit. A substantial topology variation is between the plurality of the connecting terminals and the at least one dummy conductor. A semiconductor package having the semiconductor device is also provided.