公开(公告)号：US20230361080A1

公开(公告)日：2023-11-09

申请号：US18352595

申请日：2023-07-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Kuei Hsu ,  Ming-Chih Yew ,  Shu-Shen Yeh ,  Che-Chia Yang ,  Po-Yao Lin ,  Shin-Puu Jeng

IPC: H01L25/065 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/538 ,  H01L23/00 ,  H01L23/48

CPC classification number: H01L25/0655 ,  H01L21/4857 ,  H01L21/561 ,  H01L23/3185 ,  H01L23/5383 ,  H01L23/5386 ,  H01L24/20 ,  H01L23/481 ,  H01L23/3128

Abstract: An embodiment is package structure including a first integrated circuit die, a redistribution structure bonded to the first integrated circuit die, the redistribution structure including a first metallization pattern in a first dielectric layer, the first metallization pattern including a plurality of first conductive features, each of the first conductive features including a first conductive via in the first dielectric layer and first conductive line over the first dielectric layer and electrically coupled to the respective first conductive via, each of the first conductive lines comprising a curve in a plan view, a second dielectric layer over the first dielectric layer and the first metallization pattern, and a second metallization pattern in the second dielectric layer, the second metallization pattern including a plurality of second conductive via in the second dielectric layer, each of the second conductive vias being over and electrically coupled to a respective first conductive line.

公开(公告)号：US20220181298A1

公开(公告)日：2022-06-09

申请号：US17652764

申请日：2022-02-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Kuei Hsu ,  Ming-Chih Yew ,  Shu-Shen Yeh ,  Che-Chia Yang ,  Po-Yao Lin ,  Shin-Puu Jeng

IPC: H01L25/065 ,  H01L21/48 ,  H01L21/56 ,  H01L23/538 ,  H01L23/00 ,  H01L23/31

Abstract: An embodiment is package structure including a first integrated circuit die, a redistribution structure bonded to the first integrated circuit die, the redistribution structure including a first metallization pattern in a first dielectric layer, the first metallization pattern including a plurality of first conductive features, each of the first conductive features including a first conductive via in the first dielectric layer and first conductive line over the first dielectric layer and electrically coupled to the respective first conductive via, each of the first conductive lines comprising a curve in a plan view, a second dielectric layer over the first dielectric layer and the first metallization pattern, and a second metallization pattern in the second dielectric layer, the second metallization pattern including a plurality of second conductive via in the second dielectric layer, each of the second conductive vias being over and electrically coupled to a respective first conductive line.

公开(公告)号：US11264359B2

公开(公告)日：2022-03-01

申请号：US17028629

申请日：2020-09-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Kuei Hsu ,  Ming-Chih Yew ,  Shu-Shen Yeh ,  Che-Chia Yang ,  Po-Yao Lin ,  Shin-Puu Jeng

IPC: H01L23/495 ,  H01L23/34 ,  H01L23/48 ,  H01L21/00 ,  H01L21/44 ,  H01L21/4763 ,  H01L25/065 ,  H01L23/538 ,  H01L21/56 ,  H01L21/48 ,  H01L23/31 ,  H01L23/00

Abstract: An embodiment is package structure including a first integrated circuit die, a redistribution structure bonded to the first integrated circuit die, the redistribution structure including a first metallization pattern in a first dielectric layer, the first metallization pattern including a plurality of first conductive features, each of the first conductive features including a first conductive via in the first dielectric layer and first conductive line over the first dielectric layer and electrically coupled to the respective first conductive via, each of the first conductive lines comprising a curve in a plan view, a second dielectric layer over the first dielectric layer and the first metallization pattern, and a second metallization pattern in the second dielectric layer, the second metallization pattern including a plurality of second conductive via in the second dielectric layer, each of the second conductive vias being over and electrically coupled to a respective first conductive line.

公开(公告)号：US20220020700A1

公开(公告)日：2022-01-20

申请号：US17126957

申请日：2020-12-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shu-Shen Yeh ,  Che-Chia Yang ,  Chin-Hua Wang ,  Po-Yao Lin ,  Shin-Puu Jeng ,  Chia-Hsiang Lin

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/538 ,  H01L21/48 ,  H01L21/56

Abstract: A method includes forming a first dielectric layer, forming a first redistribution line comprising a first via extending into the first dielectric layer, and a first trace over the first dielectric layer, forming a second dielectric layer covering the first redistribution line, and patterning the second dielectric layer to form a via opening. The first redistribution line is revealed through the via opening. The method further includes forming a second via in the second dielectric layer, and a conductive pad over and contacting the second via, and forming a conductive bump over the conductive pad. The conductive pad is larger than the conductive bump, with a first center of conductive pad being offsetting from a second center of the conductive bump. The second via is further offset from the second center of the conductive bump.

公开(公告)号：US11749644B2

公开(公告)日：2023-09-05

申请号：US17652764

申请日：2022-02-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Kuei Hsu ,  Ming-Chih Yew ,  Shu-Shen Yeh ,  Che-Chia Yang ,  Po-Yao Lin ,  Shin-Puu Jeng

IPC: H01L25/065 ,  H01L21/48 ,  H01L21/56 ,  H01L23/48 ,  H01L23/538 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L25/0655 ,  H01L21/4857 ,  H01L21/561 ,  H01L23/3185 ,  H01L23/481 ,  H01L23/5383 ,  H01L23/5386 ,  H01L24/20 ,  H01L23/3128

Abstract: An embodiment is package structure including a first integrated circuit die, a redistribution structure bonded to the first integrated circuit die, the redistribution structure including a first metallization pattern in a first dielectric layer, the first metallization pattern including a plurality of first conductive features, each of the first conductive features including a first conductive via in the first dielectric layer and first conductive line over the first dielectric layer and electrically coupled to the respective first conductive via, each of the first conductive lines comprising a curve in a plan view, a second dielectric layer over the first dielectric layer and the first metallization pattern, and a second metallization pattern in the second dielectric layer, the second metallization pattern including a plurality of second conductive via in the second dielectric layer, each of the second conductive vias being over and electrically coupled to a respective first conductive line.

公开(公告)号：US11670601B2

公开(公告)日：2023-06-06

申请号：US17126957

申请日：2020-12-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shu-Shen Yeh ,  Che-Chia Yang ,  Chin-Hua Wang ,  Po-Yao Lin ,  Shin-Puu Jeng ,  Chia-Hsiang Lin

IPC: H01L23/00 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L23/538 ,  H01L23/48 ,  H01L25/065

CPC classification number: H01L23/562 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/563 ,  H01L23/3107 ,  H01L23/3185 ,  H01L23/481 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/13 ,  H01L24/16 ,  H01L25/0657 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2924/18161 ,  H01L2924/351 ,  H01L2924/35121

Abstract: A method includes forming a first dielectric layer, forming a first redistribution line comprising a first via extending into the first dielectric layer, and a first trace over the first dielectric layer, forming a second dielectric layer covering the first redistribution line, and patterning the second dielectric layer to form a via opening. The first redistribution line is revealed through the via opening. The method further includes forming a second via in the second dielectric layer, and a conductive pad over and contacting the second via, and forming a conductive bump over the conductive pad. The conductive pad is larger than the conductive bump, with a first center of conductive pad being offsetting from a second center of the conductive bump. The second via is further offset from the second center of the conductive bump.

公开(公告)号：US20240363543A1

公开(公告)日：2024-10-31

申请号：US18766974

申请日：2024-07-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shu-Shen Yeh ,  Che-Chia Yang ,  Chia-Kuei Hsu ,  Po-Yao Lin ,  Shin-Puu Jeng ,  Chia-Hsiang Lin

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/768 ,  H01L23/00

CPC classification number: H01L23/5384 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/76802 ,  H01L23/5385 ,  H01L23/5386 ,  H01L24/14

Abstract: A method includes forming a first dielectric layer, forming a first redistribution line including a first via extending into the first dielectric layer, and a first trace over the first dielectric layer, forming a second dielectric layer covering the first redistribution line, and patterning the second dielectric layer to form a via opening. The first redistribution line is revealed through the via opening. The method further includes depositing a conductive material into the via opening to form a second via in the second dielectric layer, and a conductive pad over and contacting the second via, and forming a conductive bump over the conductive pad. The conductive pad is larger than the conductive bump, and the second via is offset from a center line of the conductive bump.

公开(公告)号：US20240088061A1

公开(公告)日：2024-03-14

申请号：US18517489

申请日：2023-11-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shu-Shen Yeh ,  Che-Chia Yang ,  Chin-Hua Wang ,  Po-Yao Lin ,  Shin-Puu Jeng ,  Chia-Hsiang Lin

IPC: H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/48 ,  H01L23/538 ,  H01L25/065

CPC classification number: H01L23/562 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/563 ,  H01L23/3107 ,  H01L23/3185 ,  H01L23/481 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/13 ,  H01L24/16 ,  H01L25/0657 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2924/18161 ,  H01L2924/351 ,  H01L2924/35121

Abstract: A method includes forming a first dielectric layer, forming a first redistribution line comprising a first via extending into the first dielectric layer, and a first trace over the first dielectric layer, forming a second dielectric layer covering the first redistribution line, and patterning the second dielectric layer to form a via opening. The first redistribution line is revealed through the via opening. The method further includes forming a second via in the second dielectric layer, and a conductive pad over and contacting the second via, and forming a conductive bump over the conductive pad. The conductive pad is larger than the conductive bump, with a first center of conductive pad being offsetting from a second center of the conductive bump. The second via is further offset from the second center of the conductive bump.

公开(公告)号：US20220020693A1

公开(公告)日：2022-01-20

申请号：US17126881

申请日：2020-12-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shu-Shen Yeh ,  Che-Chia Yang ,  Chia-Kuei Hsu ,  Po-Yao Lin ,  Shin-Puu Jeng ,  Chia-Hsiang Lin

IPC: H01L23/538 ,  H01L23/00 ,  H01L21/768 ,  H01L21/48

Abstract: A method includes forming a first dielectric layer, forming a first redistribution line including a first via extending into the first dielectric layer, and a first trace over the first dielectric layer, forming a second dielectric layer covering the first redistribution line, and patterning the second dielectric layer to form a via opening. The first redistribution line is revealed through the via opening. The method further includes depositing a conductive material into the via opening to form a second via in the second dielectric layer, and a conductive pad over and contacting the second via, and forming a conductive bump over the conductive pad. The conductive pad is larger than the conductive bump, and the second via is offset from a center line of the conductive bump.

公开(公告)号：US20240387339A1

公开(公告)日：2024-11-21

申请号：US18787212

申请日：2024-07-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shu-Shen Yeh ,  Che-Chia Yang ,  Chin-Hua Wang ,  Chia-Kuei Hsu ,  Po-Yao Lin ,  Shin-Puu Jeng

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/00

Abstract: A package structure and a method of forming the same are provided. The package structure includes an integrated circuit die and a redistribution structure bonded to the integrated circuit die. The redistribution structure includes a first insulating layer, a second insulating layer interposed between the first insulating layer and the integrated circuit die, and a first metallization pattern in the first insulating layer and the second insulating layer. The first metallization pattern includes a first conductive line and a first conductive via coupled to the first conductive line. The first conductive line is in the second insulating layer. The first conductive via is in the first insulating layer. The first conductive line includes a first conductive pad coupled to the first conductive via, a second conductive pad, and a curved portion connecting the first conductive pad to the second conductive pad.