公开(公告)号：US07403407B1

公开(公告)日：2008-07-22

申请号：US10266953

申请日：2002-10-08

Applicant: Sanjay M. Wanzakhade

Inventor： Sanjay M. Wanzakhade

IPC: G11C15/00

CPC classification number: G11C15/04 ,  G11C15/00

Abstract: A magnitude comparator circuit can include a bitwise comparison section that includes two passgates for each bit of two values that are compared to one another. The passgates can be enabled according to corresponding bit values of the two values.

Abstract translation: 幅度比较器电路可以包括按比例比较部分，其包括彼此比较的两个值的每个位的两个通路。 可以根据两个值的相应位值启用通行。

公开(公告)号：US20080155189A1

公开(公告)日：2008-06-26

申请号：US12072361

申请日：2008-02-25

Applicant: Dinesh Maheshwari

Inventor： Dinesh Maheshwari

IPC: G06F12/00

CPC classification number: G11C15/00

Abstract: A method and circuit to implement a match against range rule functionality. A first rule entry and a second rule entry are stored. The first rule entry includes at least two consecutive identical bits. The first rule entry represents a numerical range. A first field of a binary key is compared with the first rule entry to determine whether any of the bits of the first field are not identical. A logical result of the comparison between the first field and the first rule entry is inverted to generate a first comparison result. A second field of the binary key is compared with a second rule entry to generate a second comparison result. The first comparison result is then logically ANDed with the second comparison result to determine whether the binary key falls within the numerical range represented by the first rule entry and matches the second rule entry.

公开(公告)号：US07389377B2

公开(公告)日：2008-06-17

申请号：US11426011

申请日：2006-06-22

Applicant: Pankaj Gupta

Inventor： Pankaj Gupta

IPC: G06F12/00

CPC classification number: G11C15/00

Abstract: An integrated circuit device for processing an access control list. The integrated circuit device includes a first content addressable memory (CAM) including a plurality of CAM blocks to generate respective match indices, each match index indicating a storage location within the corresponding CAM block of an entry that matches a search key. The integrated circuit device further includes a plurality of memory arrays to receive the match indices from the CAM blocks and to output respective lookup values from storage locations indicated by the match indices, each lookup value including information that indicates an action to be taken with respect to a packet used to obtain the search key and information that indicates a priority of the action relative to actions indicated by information in others of the lookup values.

Abstract translation: 一种用于处理访问控制列表的集成电路装置。 集成电路装置包括：第一内容可寻址存储器（CAM），其包括多个CAM块以产生相应的匹配索引，每个匹配索引指示与搜索关键字匹配的条目的对应CAM块内的存储位置。 集成电路装置还包括多个存储器阵列，用于从CAM块接收匹配索引，并从由匹配索引指示的存储位置输出相应的查找值，每个查找值包括指示相对于 用于获得搜索关键字的分组和指示相对于其他查找值中由信息指示的动作的动作的优先级的信息。

公开(公告)号：US07362602B1

公开(公告)日：2008-04-22

申请号：US11501584

申请日：2006-08-08

Applicant: Anita X. Meng ,  Hariom Rai

Inventor： Anita X. Meng ,  Hariom Rai

IPC: G11C7/00

CPC classification number: G11C7/067 ,  G11C7/062 ,  G11C15/04

Abstract: A sense amplifier circuit can be coupled to a match line for receiving a match line voltage and to a low potential line for receiving a low potential voltage from a memory array. The sense amplifier circuit can include a charging circuit coupled between a power supply voltage and the match line voltage that comprises no p-channel transistors. A discharging circuit can be coupled between the low potential voltage and a ground supply voltage. An n-channel sensing device can coupled to detect a potential difference between the match line voltage and the low potential voltage.

Abstract translation: 感测放大器电路可以耦合到用于接收匹配线电压的匹配线和用于从存储器阵列接收低电位电压的低电位线。 读出放大器电路可以包括耦合在电源电压和不包括p沟道晶体管的匹配线电压之间的充电电路。 放电电路可以耦合在低电位电压和接地电源电压之间。 n沟道感测装置可以耦合以检测匹配线电压和低电位电压之间的电位差。

公开(公告)号：US07346000B1

公开(公告)日：2008-03-18

申请号：US10613628

申请日：2003-07-02

Applicant: Varadarajan Srinivasan ,  Sandeep Khanna

Inventor： Varadarajan Srinivasan ,  Sandeep Khanna

IPC: G01R31/08 ,  G06F11/00 ,  G08C15/00 ,  H04J1/16 ,  H04L1/00 ,  H04L12/26

CPC classification number: H04L41/0896 ,  H04L41/0893 ,  H04L41/5003 ,  H04L41/5067 ,  H04L43/0882 ,  H04L43/0894 ,  H04L43/16 ,  H04L47/10 ,  H04L47/12 ,  H04L47/20 ,  H04L47/2441 ,  H04L47/32

Abstract: A traffic management processor that selectively throttles individual traffic flows or particular traffic types specified in a throttle control instruction, which may also cause the traffic management processor to throttle all network traffic.

Abstract translation: 一种流量管理处理器，其选择性地节流在节流控制指令中指定的各个业务流或特定业务类型，这也可能导致业务管理处理器扼制所有网络业务。

公开(公告)号：US07324362B1

公开(公告)日：2008-01-29

申请号：US11366040

申请日：2006-03-01

Applicant: Dinesh Maheshwari

Inventor： Dinesh Maheshwari

IPC: G11C15/00

CPC classification number: G11C15/04

Abstract: A CAM cell (200) can include a compare section (206) and a configuration section (208). In a binary mode of operation, two compare data values can be driven on value lines VL1 to VL4 (216-0 to 216-3) for comparison against two stored data values. In a ternary mode of operation, one compare data value can driven on two of the value lines, while the other two value lines can be forced to a potential unrelated to a compare data value allowing for dynamic configuration between binary and ternary modes of operation.

Abstract translation: CAM单元（200）可以包括比较部分（206）和配置部分（208）。 在二进制操作模式下，可以在值行VL 1至VL 4（216-0至216-3）上驱动两个比较数据值，以便与两个存储的数据值进行比较。 在三元操作模式下，一个比较数据值可以在两个值行上驱动，而另外两个值行可以被强制为与允许二进制和三进制操作模式之间的动态配置的比较数据值无关的电位。

公开(公告)号：US07323916B1

公开(公告)日：2008-01-29

申请号：US11321412

申请日：2005-12-29

Applicant: Stefanos Sidiropoulos ,  Marc Loinaz ,  R. Shekhar Narayanaswami ,  Nikhil Acharya ,  Dean Liu

Inventor： Stefanos Sidiropoulos ,  Marc Loinaz ,  R. Shekhar Narayanaswami ,  Nikhil Acharya ,  Dean Liu

IPC: H03L7/06

CPC classification number: H03L7/0893 ,  H03K5/133 ,  H03K2005/00052 ,  H03L7/081 ,  H03L7/0895 ,  H03L7/093 ,  H03L7/0998 ,  H03L7/18

Abstract: A frequency synthesis circuit includes a phase locked loop and an interpolator circuit. The phase locked loop circuit receives a reference clock and a feedback clock and generates an output clock with a frequency based on the reference clock and the feedback clock. An interpolator circuit is coupled in the feedback path of the phase locked loop circuit. An interpolator control circuit generates an interpolator control word that specifies a variable time delay for the interpolator circuit. The interpolator circuit receives the output clock, and generates the feedback clock by introducing a variable time delay in the output clock in accordance with the interpolator control word. The time variable delay varies the frequency of the output circuit. Embodiments for frequency synthesis circuits that include a spread spectrum frequency clock generator, frequency modulators, and a fixed frequency clock generator circuit are disclosed.

Abstract translation: 频率合成电路包括锁相环和内插器电路。 锁相环电路接收参考时钟和反馈时钟，并产生基于参考时钟和反馈时钟的频率的输出时钟。 内插器电路耦合在锁相环电路的反馈路径中。 内插器控制电路产生指定内插器电路的可变时间延迟的内插器控制字。 内插器电路接收输出时钟，并根据内插器控制字在输出时钟中引入可变时间延迟来产生反馈时钟。 时间可变延迟会改变输出电路的频率。 公开了包括扩频频率时钟发生器，频率调制器和固定频率时钟发生器电路的频率合成电路的实施例。

公开(公告)号：US07277983B1

公开(公告)日：2007-10-02

申请号：US11085399

申请日：2005-03-21

Applicant: Hari Om

Inventor： Hari Om

IPC: G06F12/00 ,  G11C15/00

CPC classification number: G11C15/00

Abstract: A CAM device (100) according to an embodiment can include a control circuit (106) that can sequentially activate, with dummy operations, an increasingly larger number of CAM blocks (102-1 to 102-16) in response to a start-up circuit (104) indication until an initial number of CAM blocks is activated. A control circuit (106) can receive a user configurable block number (USER_BLK) and adjust the number of CAM blocks in a sequentially fashion, with dummy operations, until the user configurable number of CAM blocks is being activated. If a received command is targeted to less than the user configurable block number of CAM blocks, a control circuit (106) can activate, with dummy operations, an additional number of CAM blocks so that the total number of CAM blocks activate equals the user configurable block number.

Abstract translation: 根据实施例的CAM设备（100）可以包括控制电路（106），该控制电路（106）可响应于启动而以虚拟操作顺序地激活越来越多数量的CAM块（102-1至102-16） 电路（104）指示，直到初始数量的CAM块被激活。 控制电路（106）可以接收用户可配置的块号（USER_BLK），并以空操作顺序地调整CAM块的数量，直到用户可配置的CAM块的数量被激活。 如果接收到的命令被定位为小于用户可配置的块数量的CAM块，则控制电路（106）可以通过虚拟操作来激活附加数量的CAM块，使得CAM块的总数激活等于用户可配置 块号。

公开(公告)号：US07230841B1

公开(公告)日：2007-06-12

申请号：US11061259

申请日：2005-02-18

Applicant: Varadarajan Srinivasan ,  Bindiganavale S. Nataraj ,  Sandeep Khanna

Inventor： Varadarajan Srinivasan ,  Bindiganavale S. Nataraj ,  Sandeep Khanna

IPC: G11C15/00 ,  G06F12/00

CPC classification number: G11C15/04

Abstract: A content addressable memory (CAM) architecture. For one embodiment, the CAM architecture includes a plurality of rows of CAM cells, each row configured to generate match results on a corresponding match line, a number of comparand lines, each coupled to a corresponding CAM cell in each of the plurality of rows of CAM cells, a plurality of timed storage circuits, each having a data input coupled to a corresponding match line and having an enable input coupled to an enable signal line, a timing generator configured to generate an enable signal on the enable signal line, and a plurality of load elements.

Abstract translation: 内容可寻址存储器（CAM）架构。 对于一个实施例，CAM架构包括多个CAM单元行，每行被配置为在对应的匹配线上生成匹配结果，多个比较线，每个耦合到多行行中的每一行中的相应CAM单元 CAM单元，多个定时存储电路，每个具有耦合到对应匹配线的数据输入并具有耦合到使能信号线的使能输入的定时存储电路;定时发生器，被配置为在使能信号线上产生使能信号;以及 多个负载元件。

公开(公告)号：US07219187B1

公开(公告)日：2007-05-15

申请号：US10232576

申请日：2002-08-30

Applicant: Sandeep Khanna ,  James P. McDermott

Inventor： Sandeep Khanna ,  James P. McDermott

IPC: G06F12/00

CPC classification number: H04L45/00 ,  H04L45/7453

Abstract: A content addressable memory device having a search parameter table.

Abstract translation: 一种具有搜索参数表的内容可寻址存储器件。