公开(公告)号：US07282382B2

公开(公告)日：2007-10-16

申请号：US11088249

申请日：2005-03-23

Applicant: Peter Rieve ,  Konstantin Seibel ,  Michael Wagner

Inventor： Peter Rieve ,  Konstantin Seibel ,  Michael Wagner

IPC: H01L21/00

CPC classification number: H01L27/14689 ,  H01L27/14636 ,  H01L27/14692

Abstract: The invention relates to a method for producing a photodiode contact for a TFA image sensor which includes a photodiode, produced by deposition of a multilayer system and a transparent conductive contact layer on an ASIC circuit that has been coated with an intermediate metal dielectric component and that has vias in a photoactive zone which are arranged on a pixel grid. Said vias extend through the intermediate metal dielectric component and are linked with respective strip conductors of the CMOS-ASIC circuit. A pixel-grid structured barrier layer, and on top thereof a CMOS metallization, are arranged on the intermediate metal dielectric component. The aim of the invention is to improve the characteristic variables of the photodiode by simple technological means. This object is achieved by removing at least the CMOS metallization present on the CMOS-ASIC circuit in the area of the photoactive zone except for the structured barrier layer and subsequently applying the multilayer system of the photodiode and the conductive transparent contact layer to the CMOS-ASIC circuit.

Abstract translation: 本发明涉及一种用于制造用于TFA图像传感器的光电二极管接触的方法，其包括通过在已经涂覆有中间金属介电部件的ASIC电路上沉积多层系统和透明导电接触层而产生的光电二极管，并且 在光栅区中具有布置在像素网格上的通孔。 所述通孔延伸穿过中间金属电介质部件并与CMOS-ASIC电路的相应带状导体连接。 在中间金属电介质部件上布置有像素网格结构的势垒层，并且在其上方具有CMOS金属化。 本发明的目的是通过简单的技术手段改善光电二极管的特征变量。 该目的通过在除了结构化阻挡层之外的光活性区域中至少除去存在于CMOS-ASIC电路上的CMOS金属化，并且随后将光电二极管和导电透明接触层的多层系统施加到CMOS- ASIC电路。

公开(公告)号：US20070207621A1

公开(公告)日：2007-09-06

申请号：US11510130

申请日：2006-08-25

Applicant: Stefan Guenther

Inventor： Stefan Guenther

IPC: H01L21/302

CPC classification number: H01L21/823864 ,  H01L27/0922

Abstract: The invention relates to a method for the production of both MOS transistors with extremely low leakage currents at the pn junctions and logic/switching transistors, whose gates are laterally defined by spacers in a p-substrate or a p-well in an n-substrate. The aim of the invention is to provide a method for the production of MOS transistors with extremely low leakage currents that allows for parallel logic/switching transistors. This is achieved by initially carrying out an LDD ion implantation via the edges of the gates in order to form an LDD region and subsequently removing the spacers by means of an anisotropic etching step exhibiting high selectivity in relation to the gate and substrate materials, including the covering layers thereof, or by covering the MOS transistors with an extremely low leakage currents prior to isotropic spacer production such that the spacers are formed exclusively on the edges of the gates of the logic/switching transistors, while the MOS transistors with an extremely low leakage current always remain connected solely via the LDD region, and there is no high dose implantation in the S/D regions of these MOS transistors with extremely low leakage currents.

Abstract translation: 本发明涉及一种用于在pn结和逻辑/开关晶体管处产生具有极低泄漏电流的两个MOS晶体管的方法，其栅极由p衬底中的间隔物或n衬底中的p阱横向限定 。 本发明的目的是提供一种用于生产具有极低泄漏电流的MOS晶体管的方法，其允许并联逻辑/开关晶体管。 这是通过首先通过栅极的边缘进行LDD离子注入来实现的，以便形成LDD区域，并且随后通过相对于栅极和衬底材料显示高选择性的各向异性蚀刻步骤去除间隔物，包括 覆盖层，或者在各向同性间隔物生产之前以极低的漏电流覆盖MOS晶体管，使得间隔物专门形成在逻辑/开关晶体管的栅极的边缘上，而具有极低泄漏的MOS晶体管 电流始终仅通过LDD区域保持连接，并且在具有极低泄漏电流的这些MOS晶体管的S / D区域中没有高剂量注入。

公开(公告)号：US20070182604A1

公开(公告)日：2007-08-09

申请号：US10985855

申请日：2004-11-10

Applicant: Wouter Aerts ,  Roland Hug

Inventor： Wouter Aerts ,  Roland Hug

IPC: H03M1/06

CPC classification number: H04L27/2657 ,  H04L27/3881

Abstract: A signal resampler carries out a time domain interpolation of an input signal for compensating for frequency offset, such as found in an ADSL system. A sample selector interpolator carries out part of the interpolation and a second, e.g. polynomial interpolator carries out the rest of the interpolation. The time interval between samples being interpolated, can be effectively divided between a sample selector interpolator and a small second, e.g. polynomial interpolator. The complexity of the second, e.g. polynomial interpolator can be reduced or its accuracy increased if it is effectively interpolating over a much smaller time interval. The sample selector interpolator can be an oversampling arrangement, and enable the order of the second, e.g. polynomial interpolator to be reduced. Selected ones of the oversampled samples are fed to the second, e.g. polynomial interpolator to keep the operating frequency lower. A chain of upsamplers can be used to generate the oversampled samples.

Abstract translation: 信号重采样器执行用于补偿频偏的输入信号的时域插值，例如在ADSL系统中发现的。 样本选择器插值器执行插值的一部分，第二，例如， 多项式插值器执行其余的插值。 插值样本之间的时间间隔可以在样本选择器插值器和小秒针之间被有效地分割。 多项式插值器。 第二个例子的复杂性。 多项式插值器可以减少或其精度增加，如果它在更小的时间间隔内有效插值。 样本选择器插值器可以是过采样布置，并且使得第二，例如， 要减少的多项式插值器。 所选择的过采样样品​​被馈送到第二个样品。 多项式插值器保持工作频率更低。 一系列上采样器可用于生成过采样样本。

公开(公告)号：US20060206779A1

公开(公告)日：2006-09-14

申请号：US11366169

申请日：2006-03-02

Applicant: Norbert Wehn ,  Frank Kienle ,  Torben Brack

Inventor： Norbert Wehn ,  Frank Kienle ,  Torben Brack

IPC: H03M13/00

CPC classification number: H03M13/1165 ,  H03M13/1111 ,  H03M13/1137 ,  H03M13/635 ,  H03M13/6516 ,  H03M13/6563 ,  H03M13/6566

Abstract: The method is for decoding an LDPC encoded codeword, the LDPC code being represented by a bipartite graph between check nodes and variable nodes including first variable nodes and second variable nodes connected to the check nodes by a zigzag connectivity. The method includes updating messages exchanged iteratively between variable nodes and check nodes including a first variable processing phase during which all the messages from the first variable nodes to the check nodes are updated and a check nodes processing phase during which all the messages from the check nodes to the first variable nodes are updated. The check nodes processing phase further includes updating all the messages from the second variable nodes to the check nodes, and directly passing an updated message processed by a check node to the next check node through the zigzag connectivity.

Abstract translation: 该方法用于对LDPC编码码字进行解码，该LDPC码由校验节点和包括第一变量节点的可变节点和通过之字形连接连接到校验节点的第二可变节点之间的二分图表示。 该方法包括更新在可变节点和校验节点之间迭代地交换的消息，包括第一可变处理阶段，在该第一可变处理阶段期间来自第一变量节点到校验节点的所有消息被更新，以及校验节点处理阶段，在该阶段期间来自校验节点的所有消息 对第一个变量节点进行更新。 检查节点处理阶段还包括将来自第二变量节点的所有消息更新为校验节点，并且通过Z字形连接将直接由检查节点处理的更新消息传递到下一校验节点。

公开(公告)号：US07099377B2

公开(公告)日：2006-08-29

申请号：US10116760

申请日：2002-04-03

Applicant: Friedbert Berens ,  Timo Roman

Inventor： Friedbert Berens ,  Timo Roman

IPC: H04B1/69

CPC classification number: H04B1/7105 ,  H04B1/7107

Abstract: The method of interference cancellation in a CDMA wireless communication system comprises receiving an incident digital signal containing a user signal transmitted on a CDMA user physical channel and an interfering signal, projecting said incident digital signal onto a projection space orthogonal to the space containing said interfering signal, filtering said projected signal with a filter matched to the CDMA user physical channel for detecting the data contained in said user signal.

公开(公告)号：US07054349B2

公开(公告)日：2006-05-30

申请号：US10255741

申请日：2002-09-26

Applicant: Chiara Cattaneo ,  Didier Helal ,  Thierry Arnaud ,  Fritz Lebowsky ,  Régis Cattenoz

Inventor： Chiara Cattaneo ,  Didier Helal ,  Thierry Arnaud ,  Fritz Lebowsky ,  Régis Cattenoz

IPC: H04B1/707

CPC classification number: H04B1/7183 ,  H04B1/71637

Abstract: An incident pulse signal of the ultra wideband type conveys digital information that is coded using pulses having a known theoretical shape. A decoding device includes an input for receiving the incident signal, and for delivering a base signal. A comparator receives the base signal and delivers an intermediate signal representative of the sign of the base signal with respect to a reference. A sampling circuit samples the intermediate signal for delivering a digital signal. A digital processing circuit correlates the digital signal with a reference correlation signal corresponding to a theoretical base signal arising from the reception of a theoretical pulse having the known theoretical shape.

公开(公告)号：US06980822B2

公开(公告)日：2005-12-27

申请号：US10000612

申请日：2001-10-24

Applicant: Patrick Conti ,  Friedbert Berens

Inventor： Patrick Conti ,  Friedbert Berens

IPC: H04J13/00 ,  H04B7/005 ,  H04B7/26 ,  H04B7/00

CPC classification number: H04W52/52

Abstract: A cellular telephone includes a plurality of power amplifiers having a common operating region. If one of the amplifiers has to be deselected, a desired moment for the switching to another amplifier is defined based upon a predetermined transmission interrupt criterion. The power continues to be adjusted with the currently selected amplifier until the instant of switch over. Switching to the other amplifier may then be performed after the transmission has been interrupted.

Abstract translation: 蜂窝电话包括具有公共操作区域的多个功率放大器。 如果必须取消其中一个放大器，则基于预定的传输中断标准来定义用于切换到另一放大器的所需时刻。 电源继续使用当前选择的放大器进行调整，直到切换为止。 然后可以在传输中断之后切换到另一个放大器。

公开(公告)号：US20050278603A1

公开(公告)日：2005-12-15

申请号：US10653721

申请日：2003-09-02

Applicant: Friedbert Berens ,  Gerd Kreiselmaier

Inventor： Friedbert Berens ,  Gerd Kreiselmaier

IPC: G06F11/08 ,  G06F11/10 ,  H03M13/29 ,  H03M13/41 ,  H04L1/00 ,  H03M13/00

CPC classification number: H03M13/3905 ,  H03M13/2782 ,  H03M13/2903 ,  H03M13/2957 ,  H03M13/3922 ,  H03M13/3927 ,  H03M13/4107

Abstract: A combined decoder reuses input/output RAM of a turbo-code decoding circuit as alpha-RAM or beta-RAM for a convolutional code decoding circuit. Additional operational units are used for both turbo-coding and convolutional coding. An effective harware folding scheme permits calculation of 256 states serially on 8 ACS units.

Abstract translation: 组合解码器将turbo码解码电路的输入/输出RAM重用为卷积码解码电路的α-RAM或β-RAM。 额外的操作单元用于turbo编码和卷积编码。 有效的折叠方案允许在8个ACS单元上串行计算256个状态。

公开(公告)号：US06954618B2

公开(公告)日：2005-10-11

申请号：US10253769

申请日：2002-09-24

Applicant: Corinne Bonhomme

Inventor： Corinne Bonhomme

IPC: H04J1/00 ,  H04B1/707 ,  H04B7/26 ,  H04L25/02 ,  H04B15/00

CPC classification number: H04L25/0204 ,  H04B1/71057

Abstract: First estimations of the fading coefficients of a multi-path transmission channel are carried out in the sense of maximum likelihood. Sets of Wiener filter coefficients are stored according to predetermined speeds of movement of the mobile terminal and predetermined power levels of the signal. The real speed of the mobile terminal is estimated and the power of the signal for each path is measured. From this, a set of Wiener filter coefficients is derived with which the first estimations are filtered to obtain the final estimation of the fading coefficients.

Abstract translation: 在多径传输信道的衰落系数的第一估计是在最大似然的意义上进行的。 维纳滤波器系数的集合根据移动终端的预定移动速度和信号的预定功率电平来存储。 估计移动终端的实际速度，并测量每个路径的信号功率。 从此，导出一组维纳滤波器系数，利用该组合对第一估计进行滤波以获得衰落系数的最终估计。

公开(公告)号：US20050190736A1

公开(公告)日：2005-09-01

申请号：US11037504

申请日：2005-01-18

Applicant: Julien Zory ,  Filippo Speziali

Inventor： Julien Zory ,  Filippo Speziali

IPC: H03M13/27 ,  H03M13/29 ,  H04B7/216

CPC classification number: H03M13/6566 ,  H03M13/2771 ,  H03M13/2957 ,  H03M13/3972

Abstract: A device for processing data to be interleaved and stored in target memories includes N interleaving buffers, N producers, and N cells. Each cell includes a register bank of size W, and a delay circuit. The variable M defines a maximum number of concurrent write operations supported per time step W, and defines a maximum buffer size. These parameters are chosen to reflect a standard case. At any time step, each of the N interleaving buffers receives m log-likelihood ratio (LLR) inputs and writes up to M of these into the register banks. When m is larger than M, m-M producers are delayed by the delay circuit. When a buffer overflow occurs (more than W LLRs values), m producers are delayed by the delay circuit. One LLR value is fetched from the register bank and is written in an SRAM interleaving memory.

Abstract translation: 用于处理要被交织并存储在目标存储器中的数据的装置包括N个交织缓冲器，N个生成器和N个单元。 每个单元包括大小为W的寄存器组和延迟电路。 变量M定义每个时间步长W支持的最大并发写操作数，并定义最大缓冲区大小。 选择这些参数以反映标准情况。 在任何时间步长中，N个交织缓冲器中的每一个接收到m个对数似然比（LLR）输入，并将这些输入写入到寄存器组中。 当m大于M时，m-M生成器被延迟电路延迟。 当缓冲区溢出发生（超过W LLR值）时，m个生成器被延迟电路延迟。 从寄存器组中提取一个LLR值，并写入SRAM交错存储器。