公开(公告)号：US20120001655A1

公开(公告)日：2012-01-05

申请号：US13096297

申请日：2011-04-28

Applicant: Luca CICCARELLI ,  Roberto Canegallo ,  Claudio Mucci ,  Massimiliano Innocenti ,  Valentina Nardone

Inventor： Luca CICCARELLI ,  Roberto Canegallo ,  Claudio Mucci ,  Massimiliano Innocenti ,  Valentina Nardone

IPC: H03K19/0948 ,  H01L27/088 ,  H01L21/8234 ,  H01L27/092

CPC classification number: G06F17/5068

Abstract: A circuit base cell is for implementing an engineering change order (ECO) obtained on a semiconductor substrate. The base cell may include a PMOS transistor having a first active region obtained in a first diffusion P+ layer implanted in an N-well provided for on the substrate, and an NMOS transistor having a second active region obtained in a second diffusion N+ layer implanted on the substrate in such a manner as to be electrically insulated from the first diffusion P+ layer. The cell may be characterized in that the active regions and the diffusion layers are aligned therebetween with respect to a reference axis and they are extended symmetrically in the direction orthogonal to the axis. A first and a second width may be associated with the active regions and to the diffusion layers, respectively. The first and second width may be greater than a width of the cell, which is equivalent to a pitch of the standard minimum cell.

Abstract translation: 电路基座用于实现在半导体衬底上获得的工程改变顺序（ECO）。 基体单元可以包括具有第一有源区的PMOS晶体管，该第一有源区在植入在衬底上提供的N阱中的第一扩散P +层中，以及NMOS晶体管，其具有在第二扩散N +层中所获得的第二有源区， 该衬底以与第一扩散P +层电绝缘的方式。 电池的特征在于有源区域和扩散层相对于参考轴线在其间对准，并且它们在与轴线正交的方向上对称延伸。 第一和第二宽度可以分别与有源区域和扩散层相关联。 第一和第二宽度可以大于单元的宽度，其等于标准最小单元的间距。

公开(公告)号：US20110157975A1

公开(公告)日：2011-06-30

申请号：US12968522

申请日：2010-12-15

Applicant: Marco PASOTTI ,  Marcella CARISSIMI ,  Davide LENA

Inventor： Marco PASOTTI ,  Marcella CARISSIMI ,  Davide LENA

IPC: G11C16/06 ,  G11C16/04

CPC classification number: G11C16/0433 ,  G11C2216/10

Abstract: An embodiment of a non-volatile memory device integrated in a chip of semiconductor material is proposed. The memory device includes a plurality of memory cells. Each memory cell includes a first well and a second well of first type of conductivity that are formed in an insulating region of a second type of conductivity. The memory cell further includes a first, a second, a third and a fourth region of the second type of conductivity that are formed in the first well; these regions define a sequence of a first selection transistor of MOS type, a storage transistor of floating gate MOS type, and a second selection transistor of MOS type that are connected in series. The first region is short-circuited to the first well. Moreover, the memory device includes a first gate of the first selection transistor, a second gate of the second selection transistor, and a floating gate of the storage transistor. A control gate of the storage transistor is formed in the second well; the control gate is capacitively coupled with the floating gate.

Abstract translation: 提出了集成在半导体材料芯片中的非易失性存储器件的实施例。 存储装置包括多个存储单元。 每个存储单元包括形成在第二导电类型的绝缘区域中的第一类导电性的第一阱和第二阱。 存储单元还包括形成在第一阱中的第二导电类型的第一，第二，第三和第四区域; 这些区域定义了串联连接的MOS型的第一选择晶体管，浮置栅极MOS型的存储晶体管和MOS型的第二选择晶体管的序列。 第一个地区与第一个井短路。 此外，存储器件包括第一选择晶体管的第一栅极，第二选择晶体管的第二栅极和存储晶体管的浮置栅极。 存储晶体管的控制栅极形成在第二阱中; 控制栅极与浮动栅极电容耦合。

公开(公告)号：US20110157927A1

公开(公告)日：2011-06-30

申请号：US12978841

申请日：2010-12-27

Applicant: Claudio Adragna ,  Aldo Vittorio Novelli ,  Christian Leone Santoro

Inventor： Claudio Adragna ,  Aldo Vittorio Novelli ,  Christian Leone Santoro

IPC: H02M3/335

CPC classification number: H02M3/3376 ,  Y02B70/1433

Abstract: A control device for a resonant converter, the control device including a first circuit to integrate at least one signal indicating a half wave of a current circulating in a primary winding of a transformer; the first circuit is structured to generate at least a control signal of the switching circuit depending on the integrated signal. The control device includes a second circuit to impose the equality of a switching-on time period of the first and second switches.

Abstract translation: 一种用于谐振转换器的控制装置，所述控制装置包括：第一电路，用于积分表示在变压器的初级绕组中循环的电流的半波的至少一个信号; 第一电路被构造成根据积分信号产生至少一个开关电路的控制信号。 控制装置包括施加第一和第二开关的接通时间段相等的第二电路。

公开(公告)号：US20110156789A1

公开(公告)日：2011-06-30

申请号：US12980486

申请日：2010-12-29

Applicant: Juri Giovannone ,  Roberto Giorgio Bardelli ,  Giovanni Cremonesi

Inventor： Juri Giovannone ,  Roberto Giorgio Bardelli ,  Giovanni Cremonesi

IPC: H03K5/13

CPC classification number: H03L7/0812 ,  H03L7/0814 ,  H03L7/087 ,  H03L7/091

Abstract: A control system for a phase generator including a delay block including delay units, and first and second multiplexers configured to receive output signals of each of the delay units and to respectively supply first and second output signals. The control system may include a controller configured to drive the first multiplexer and the second multiplexer respectively with a first select signal and a second select signal, a detection module configured to detect a phase difference between the first output signal and the second output signal and to generate a corresponding digital phase shift signal, the detection module including a phase comparator, and a Time-Digital converter circuit coupled thereto and having logic elements configured to generate the digital phase shift signal, and a logic circuit connected to the detection module and configured to process the digital phase shift signal and to generate a signal indicative of a control executed.

Abstract translation: 一种用于相位发生器的控制系统，包括包括延迟单元的延迟块，以及第一和第二多路复用器，被配置为接收每个延迟单元的输出信号并分别提供第一和第二输出信号。 控制系统可以包括控制器，其被配置为分别用第一选择信号和第二选择信号驱动第一多路复用器和第二多路复用器，检测模块被配置为检测第一输出信号和第二输出信号之间的相位差，并且 产生相应的数字相移信号，该检测模块包括相位比较器和耦合到其上的时数数字转换器电路，并具有被配置为产生数字相移信号的逻辑元件，以及连接到检测模块的逻辑电路， 处理数字相移信号并产生指示执行控制的信号。

公开(公告)号：US20110148482A1

公开(公告)日：2011-06-23

申请号：US12973427

申请日：2010-12-20

Applicant: Alberto GUSSONI ,  Ambrogio Bogani ,  Luigino D'Alessio ,  Paolo Pascale

Inventor： Alberto GUSSONI ,  Ambrogio Bogani ,  Luigino D'Alessio ,  Paolo Pascale

IPC: H03L7/00

CPC classification number: G06F1/26 ,  G06K19/0701

Abstract: A method is for choosing a mode out of a set of functioning modes of an integrated circuit (IC) device powered from different supply voltages from respective supply nodes. The IC device may include a mode pin for determining a functioning mode of the device, an internal control circuit coupled to the supply nodes and to the mode pin for sensing an electrical value on the mode pin and to start the IC device in a respective functioning mode depending on the supply node that is powered first. The method may include identifying the different supply voltage that first exceeds a threshold voltage, when the internal control circuit is powered, sensing the electrical value on the mode pin, and powering circuits of the IC device from the different supply voltage that first exceeded the threshold voltage and starting the device in a functioning mode determined by a value of the electrical value sensed on the mode pin and by the different supply voltage that first exceeded the voltage threshold.

Abstract translation: 一种用于从由各个供应节点的不同电源电压供电的集成电路（IC）装置的一组功能模式中选择模式的方法。 IC器件可以包括用于确定器件的功能模式的模式引脚，耦合到电源节点的内部控制电路和用于感测模式引脚上的电气值的模式引脚，并且在相应的功能中启动IC器件 模式取决于第一个供电节点。 该方法可以包括：当内部控制电路通电时，识别出不同的电源电压，该电源电压首先超过阈值电压，感测模式引脚上的电气值，以及从首先超过阈值的不同电源电压为IC器件的电路供电 在由模式引脚上检测到的电气值确定的功能模式下以及首先超过电压阈值的不同电源电压启动器件。

公开(公告)号：US20110140769A1

公开(公告)日：2011-06-16

申请号：US12965500

申请日：2010-12-10

Applicant: Andrea Visconti ,  Paolo Angelini

Inventor： Andrea Visconti ,  Paolo Angelini

IPC: G05F1/10

CPC classification number: G05F3/30

Abstract: A circuit for generating a reference electrical quantity, including: a first bipolar transistor and a second bipolar transistor having the base terminals connected to one another and to a common node; a first resistor connected to the emitter terminal of the second bipolar transistor; a first mirror circuit and a second mirror circuit connected to the first and second bipolar transistors, which receive, respectively, a first current and a second current and generate, respectively, a first mirrored current and a second mirrored current; a first output stage, which generates the reference electrical quantity as a function of the first and second mirrored currents; and a second resistor connected to the common node. The first current is a function of the current in the first resistor, whilst the second current is a function of the current in the second resistor.

Abstract translation: 一种用于产生参考电量的电路，包括：第一双极晶体管和第二双极晶体管，其具有彼此连接的基极和公共节点; 连接到所述第二双极晶体管的发射极端子的第一电阻器; 连接到第一和第二双极晶体管的第一镜电路和第二镜电路分别接收第一电流和第二电流并分别产生第一镜像电流和第二镜像电流; 第一输出级，其产生作为第一和第二镜像电流的函数的参考电量; 以及连接到公共节点的第二电阻器。 第一电流是第一电阻器中的电流的函数，而第二电流是第二电阻器中的电流的函数。

公开(公告)号：US20110095610A1

公开(公告)日：2011-04-28

申请号：US12893848

申请日：2010-09-29

Applicant: Pierangelo CONFALONIERI ,  Federico GUANZIROLI ,  Marco ZAMPROGNO

Inventor： Pierangelo CONFALONIERI ,  Federico GUANZIROLI ,  Marco ZAMPROGNO

IPC: H02J3/00

CPC classification number: H03K17/162 ,  H03M1/0845 ,  H03M1/12 ,  H03M1/66 ,  Y10T307/50

Abstract: A system includes analog supply circuitry providing first and second analog potentials. A switch module assumes first or second states to enable and inhibit transfer of an analog electrical signal from a source module to a user module based upon a driving electrical signal. A driving device drives, based upon the driving electrical signal, a control terminal of the switch module, allowing the switch module to assume the first or second state. The driving device allows the switch module to make a first driving transition from the first state to the second state, and a second driving transition from the second state to the first state. The driving device alternately connects the control terminal to a first reference potential, during the first state, and to a second reference potential, during the second state. The driving device connects the control terminal of the switch module to a third reference potential electrically distinct from the first and the second analog potentials, during each of the time intervals associated to the first or second driving transitions of the switch module.

Abstract translation: 系统包括提供第一和第二模拟电位的模拟电源电路。 开关模块基于驱动电信号，假设第一或第二状态来启用和禁止模拟电信号从源模块传送到用户模块。 驱动装置基于驱动电信号驱动开关模块的控制端子，允许开关模块呈现第一或第二状态。 驱动装置允许开关模块进行从第一状态到第二状态的第一驱动转变，以及从第二状态到第一状态的第二驱动转变。 在第二状态期间，驱动装置在第一状态期间交替地将控制端子连接到第一参考电位，并将第二参考电位交替地连接到第二参考电位。 在与开关模块的第一或第二驱动转换相关联的每个时间间隔期间，驱动装置将开关模块的控制端子连接到与第一和第二模拟电位电不同的第三参考电位。

公开(公告)号：US20110084412A1

公开(公告)日：2011-04-14

申请号：US12900994

申请日：2010-10-08

Applicant: Emanuele Brenna ,  Antonio Di Franco

Inventor： Emanuele Brenna ,  Antonio Di Franco

IPC: H01L23/58 ,  H01L21/78

CPC classification number: H01L23/544 ,  H01L21/82 ,  H01L2223/54406 ,  H01L2223/54413 ,  H01L2223/5442 ,  H01L2223/54433 ,  H01L2223/5448 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A solution for indexing electronic devices includes corresponding electronic device including a die integrating an electronic circuit, the die having at least one index including a reference defining an ordered alignment of a plurality of locations on the die and a marker for defining a value of the index according to an arrangement of the marker with respect to the reference. In one embodiment, the marker includes a plurality of markers each one arranged at a selected one of the locations, the selected location of the marker defining a value of a digit associated with a corresponding power of a base higher than 2 within a number in a positional notation in the base representing the value of the index.

Abstract translation: 用于索引电子设备的解决方案包括相应的电子设备，其包括集成电子电路的模具，所述裸片具有至少一个索引，所述至少一个索引包括限定所述芯片上的多个位置的有序对准的参考线和用于定义所述索引的值的标记 根据该标记相对于该参照的布置。 在一个实施例中，标记包括多个标记，每个标记被布置在选定的一个位置处，标记的所选择的位置定义与一个数字中的高于2的基数的相应功率相关联的数字的值 表示索引值的基数中的位置符号。

公开(公告)号：US20100322638A1

公开(公告)日：2010-12-23

申请号：US12790659

申请日：2010-05-28

Applicant: Alberto Scandurra ,  Giuseppe Guarnaccia ,  Salvatore Pisasale ,  Fabio Zito

Inventor： Alberto Scandurra ,  Giuseppe Guarnaccia ,  Salvatore Pisasale ,  Fabio Zito

IPC: H04B10/04 ,  H04B10/06

CPC classification number: H04B10/506

Abstract: An on-chip receiver for flows of information conveyed to a target via optical signals with different wavelengths includes a plurality of photo-detector modules, each sensitive to a different wavelength, for converting a respective optical signal at input into an electrical signal, a plurality of de-serialization circuits acting on the electrical signals for converting into packet traffic the flows of information received via the photo-detector modules, and an arbitration node acting on the packet traffic to enable a single packet at a time to achieve the target.

Abstract translation: 用于经由具有不同波长的光信号传送到目标的信息流的片上接收器包括多个光敏检测器模块，每个光检测器模块对不同波长敏感，用于将输入处的各个光信号转换为电信号，多个 作用于电信号的解串行化电路，用于将经由光检测器模块接收的信息流转换成分组业务，以及作用于分组业务的仲裁节点，以一次实现单个分组来实现目标。

公开(公告)号：US20100318822A1

公开(公告)日：2010-12-16

申请号：US12815004

申请日：2010-06-14

Applicant: Alberto Scandurra ,  Alan LLoyd ,  Raffaele Guarrasi

Inventor： Alberto Scandurra ,  Alan LLoyd ,  Raffaele Guarrasi

IPC: G06F1/32 ,  G06F1/12

CPC classification number: G06F1/3203 ,  G06F1/3243 ,  G06F1/3287 ,  Y02D10/152 ,  Y02D10/171

Abstract: A System-on-Chip may include initiators, targets exchanging information with the initiators, and a control module. The control module may be configured to selectively set to one of different reduced power consumption modes each of the initiators and each of the targets based upon external reduced power consumption instructions, and selectively wake-up from the reduced power consumption mode each initiator and each target.

Abstract translation: 片上系统可以包括发起者，与发起者交换信息的目标，以及控制模块。 控制模块可以被配置为基于外部减少功耗指令，选择性地将每个启动器和每个目标设置为不同的降低的功耗模式之一，并且从降低的功耗模式中选择性地唤醒每个启动器和每个目标 。