公开(公告)号：US08693256B2

公开(公告)日：2014-04-08

申请号：US12975055

申请日：2010-12-21

Applicant: Marco Pasotti ,  Davide Lena ,  Fabio De Santis

Inventor： Marco Pasotti ,  Davide Lena ,  Fabio De Santis

IPC: G11C11/34

CPC classification number: G11C16/0433 ,  G11C16/0491 ,  G11C16/3418 ,  G11C2216/10

Abstract: A non-volatile memory device integrated in a chip of semiconductor material. An embodiment of a memory device includes a plurality of memory cells. Each memory cell includes a first well and a second well of a first type of conductivity that are formed in an insulating region of a second type of conductivity. The memory cell further includes a first, a second, and a third region of the second type of conductivity that are formed in the first well; these regions define a selection transistor of MOS type and a storage transistor of floating gate MOS type that are coupled in series. Moreover, the memory device includes a selection gate of the selection transistor, a floating gate of the storage transistor, and a control gate of the storage transistor formed in the second well; the control gate is capacitively coupled with the floating gate.

Abstract translation: 集成在半导体材料芯片中的非易失性存储器件。 存储器件的实施例包括多个存储器单元。 每个存储单元包括形成在第二导电类型的绝缘区域中的第一导电类型的第一阱和第二阱。 存储单元还包括形成在第一阱中的第二类型导电性的第一，第二和第三区域; 这些区域限定了串联耦合的MOS型选择晶体管和浮置栅极MOS型存储晶体管。 此外，存储器件包括选择晶体管的选择栅极，存储晶体管的浮置栅极和形成在第二阱中的存储晶体管的控制栅极; 控制栅极与浮动栅极电容耦合。

公开(公告)号：US08619469B2

公开(公告)日：2013-12-31

申请号：US12968522

申请日：2010-12-15

Applicant: Marco Pasotti ,  Marcella Carissimi ,  Davide Lena

Inventor： Marco Pasotti ,  Marcella Carissimi ,  Davide Lena

IPC: G11C16/04

CPC classification number: G11C16/0433 ,  G11C2216/10

Abstract: An embodiment of a non-volatile memory device integrated in a chip of semiconductor material is proposed. The memory device includes a plurality of memory cells. Each memory cell includes a first well and a second well of first type of conductivity that are formed in an insulating region of a second type of conductivity. The memory cell further includes a first, a second, a third and a fourth region of the second type of conductivity that are formed in the first well; these regions define a sequence of a first selection transistor of MOS type, a storage transistor of floating gate MOS type, and a second selection transistor of MOS type that are coupled in series. The first region is short-circuited to the first well. Moreover, the memory device includes a first gate of the first selection transistor, a second gate of the second selection transistor, and a floating gate of the storage transistor. A control gate of the storage transistor is formed in the second well; the control gate is capacitively coupled with the floating gate.

Abstract translation: 提出了集成在半导体材料芯片中的非易失性存储器件的实施例。 存储装置包括多个存储单元。 每个存储单元包括形成在第二导电类型的绝缘区域中的第一类导电性的第一阱和第二阱。 存储单元还包括形成在第一阱中的第二导电类型的第一，第二，第三和第四区域; 这些区域限定了串联耦合的MOS型第一选择晶体管，浮栅MOS型存储晶体管和MOS型第二选择晶体管的序列。 第一个地区与第一个井短路。 此外，存储器件包括第一选择晶体管的第一栅极，第二选择晶体管的第二栅极和存储晶体管的浮置栅极。 存储晶体管的控制栅极形成在第二阱中; 控制栅极与浮动栅极电容耦合。

公开(公告)号：US20110157975A1

公开(公告)日：2011-06-30

申请号：US12968522

申请日：2010-12-15

Applicant: Marco PASOTTI ,  Marcella CARISSIMI ,  Davide LENA

Inventor： Marco PASOTTI ,  Marcella CARISSIMI ,  Davide LENA

IPC: G11C16/06 ,  G11C16/04

CPC classification number: G11C16/0433 ,  G11C2216/10

Abstract: An embodiment of a non-volatile memory device integrated in a chip of semiconductor material is proposed. The memory device includes a plurality of memory cells. Each memory cell includes a first well and a second well of first type of conductivity that are formed in an insulating region of a second type of conductivity. The memory cell further includes a first, a second, a third and a fourth region of the second type of conductivity that are formed in the first well; these regions define a sequence of a first selection transistor of MOS type, a storage transistor of floating gate MOS type, and a second selection transistor of MOS type that are connected in series. The first region is short-circuited to the first well. Moreover, the memory device includes a first gate of the first selection transistor, a second gate of the second selection transistor, and a floating gate of the storage transistor. A control gate of the storage transistor is formed in the second well; the control gate is capacitively coupled with the floating gate.

Abstract translation: 提出了集成在半导体材料芯片中的非易失性存储器件的实施例。 存储装置包括多个存储单元。 每个存储单元包括形成在第二导电类型的绝缘区域中的第一类导电性的第一阱和第二阱。 存储单元还包括形成在第一阱中的第二导电类型的第一，第二，第三和第四区域; 这些区域定义了串联连接的MOS型的第一选择晶体管，浮置栅极MOS型的存储晶体管和MOS型的第二选择晶体管的序列。 第一个地区与第一个井短路。 此外，存储器件包括第一选择晶体管的第一栅极，第二选择晶体管的第二栅极和存储晶体管的浮置栅极。 存储晶体管的控制栅极形成在第二阱中; 控制栅极与浮动栅极电容耦合。

公开(公告)号：US20110157972A1

公开(公告)日：2011-06-30

申请号：US12975155

申请日：2010-12-21

Applicant: Marco PASOTTI ,  Davide LENA ,  Giancarlo PISONI ,  Fabrizio TORRICELLI ,  Zsolt M. KOVACS-VAJNA

Inventor： Marco PASOTTI ,  Davide LENA ,  Giancarlo PISONI ,  Fabrizio TORRICELLI ,  Zsolt M. KOVACS-VAJNA

IPC: G11C16/04 ,  G11C16/12 ,  G11C16/14

CPC classification number: G11C16/0441 ,  G11C16/045 ,  G11C2216/10

Abstract: An embodiment of non-volatile memory device integrated in a chip of semiconductor material is proposed. The memory includes at least one sector of a plurality of memory cells; each sector includes a storage region of a first type of conductivity and a further storage region of a second type of conductivity. Each memory cell includes a first region and a second region of the second type of conductivity, which are formed in the storage region for defining a storage transistor of floating gate MOS type of the first type of conductivity; the memory cell likewise includes a further first region and a further second region of the first type of conductivity, which are formed in the further storage region for defining a further storage transistor of floating gate MOS type of the second type of conductivity. The memory cell also includes a common floating gate of the storage transistor and the further storage transistor. The memory device further includes programming means for programming each memory cell individually by programming the corresponding floating gate through the corresponding storage transistor, and erasing means for erasing each memory cell individually by erasing the corresponding floating gate through the corresponding further storage transistor.

Abstract translation: 提出了集成在半导体材料芯片中的非易失性存储器件的实施例。 存储器包括多个存储器单元的至少一个扇区; 每个扇区包括第一导电类型的存储区域和第二导电类型的另外的存储区域。 每个存储单元包括形成在存储区域中的第一类型的第一导电类型的第一区域和第二区域，用于限定第一导电类型的浮栅MOS型存储晶体管; 存储单元同样包括第一导电类型的另一第一区域和另一第二区域，其形成在另外的存储区域中，用于限定第二导电类型的浮栅MOS型的另一存储晶体管。 存储单元还包括存储晶体管的公共浮置栅极和另外的存储晶体管。 存储装置还包括编程装置，用于通过对相应的存储晶体管对相应的浮置栅格进行编程来分别对每个存储单元进行编程;以及擦除装置，用于通过相应的另外的存储晶体管擦除相应的浮置栅，来分别擦除每个存储单元。

公开(公告)号：US07251705B2

公开(公告)日：2007-07-31

申请号：US10768743

申请日：2004-01-29

Applicant: Marco Pasotti ,  Michele Borgatti ,  Pier Luigi Rolandi

Inventor： Marco Pasotti ,  Michele Borgatti ,  Pier Luigi Rolandi

IPC: G06F12/00

CPC classification number: G11C16/30

Abstract: An application-specific embeddable flash memory having three content-specific I/O ports and delivering a peak read throughput of 1.2 GB/s. The memory is combined with a special automatic programming gate voltage ramp generator circuit having a programming rate of 1 Mbyte/s for non-volatile storage of code, data, and embedded FPGA bit stream configurations. The test chip uses a NOR-type 0.18 μm flash embedded technology with 1.8V power supply, two poly, six metal and memory cell size of 0.35 μm2.

Abstract translation: 具有三个特定于内容的I / O端口并具有1.2 GB / s的峰值读取吞吐量的特定于应用的嵌入式闪存。 该存储器与用于代码，数据和嵌入式FPGA位流配置的非易失性存储的具有1兆字节/秒的编程速率的专用自动编程门电压斜坡发生器电路组合。 测试芯片采用NOR型0.18 mum闪存嵌入式技术，具有1.8V电源，两个聚六金属和存储单元尺寸为0.35 mum 2。

公开(公告)号：US20060226873A1

公开(公告)日：2006-10-12

申请号：US11321732

申请日：2005-12-28

Applicant: Guido De Sandre ,  Marco Poles ,  Marco Pasotti

Inventor： Guido De Sandre ,  Marco Poles ,  Marco Pasotti

IPC: H03K19/0175

CPC classification number: H03K19/018528 ,  H03K19/01707 ,  H03K19/01721

Abstract: Level shifter translator of the type comprising at least one first transistor and one second MOS transistor belonging to respective circuit branches connected with a first common conduction terminal and connected towards a first potential reference and receiving, on the respective conduction terminals, input differential voltages, the first and the second transistor have respective circuit branches referring to a biasing circuit with current mirror, a third transistor allows to couple the second transistor to said biasing circuit, an inverter connected to an output of said the circuit with the output driving the third transistor.

公开(公告)号：US6163483A

公开(公告)日：2000-12-19

申请号：US447531

申请日：1999-11-23

Applicant: Marco Pasotti ,  Roberto Canegallo ,  Giovanni Guaitini ,  Pier Luigi Rolandi

Inventor： Marco Pasotti ,  Roberto Canegallo ,  Giovanni Guaitini ,  Pier Luigi Rolandi

IPC: G11C16/12 ,  G11C7/00

CPC classification number: G11C16/12

Abstract: A circuit having a current mirror circuit with a first node and a second node connected, respectively, to a controllable current source and to a common node connected to the drain terminals of selected memory cells. A first operational amplifier has inputs connected to the first node and the second node, and an output connected to a control terminal of the selected memory cells and forming the circuit output. A second operational amplifier has a first input connected to a ramp generator, a second input connected to the circuit output, and an output connected to a control input of the controllable current source. Thereby, two negative feedback loops keep the drain terminals of the selected memory cells at a voltage value sufficient for programming, and feed the control terminal of the memory cells with a ramp voltage that causes writing of the selected memory cells. The presence of a bias source between the second node and the common node enables use of the same circuit also during reading.

Abstract translation: 一种具有电流镜电路的电路，具有第一节点和第二节点，分别连接到可控电流源和连接到所选存储器单元的漏极端子的公共节点。 第一运算放大器具有连接到第一节点和第二节点的输入，以及连接到所选择的存储器单元的控制端子并形成电路输出的输出。 第二运算放大器具有连接到斜坡发生器的第一输入端，连接到电路输出端的第二输入端，以及连接到可控电流源的控制输入端的输出端。 因此，两个负反馈环路将所选择的存储单元的漏极端子保持在足以编程的电压值，并且以导致所选择的存储单元写入的斜坡电压馈送存储单元的控制端子。 在第二节点和公共节点之间存在偏置源，使得在读取期间也可以使用相同的电路。

公开(公告)号：US06011715A

公开(公告)日：2000-01-04

申请号：US185906

申请日：1998-11-03

Applicant: Marco Pasotti ,  Pier Luigi Rolandi ,  Roberto Canegallo ,  Danilo Gerna ,  Ernestina Chioffi

Inventor： Marco Pasotti ,  Pier Luigi Rolandi ,  Roberto Canegallo ,  Danilo Gerna ,  Ernestina Chioffi

IPC: G11C11/56 ,  G11C7/00

CPC classification number: G11C11/5621 ,  G11C11/5628

Abstract: A programming method for a nonvolatile memory includes the steps of: a) determining a current value of the threshold voltage; b) acquiring a target value of the threshold voltage; c) calculating a first number of gate voltage pulses necessary to take the threshold voltage from the current value to the target value; d) applying a second number of consecutive voltage pulses to the gate terminal of the cell, the second number being correlated to the first number and having a uniformly increasing amplitude; e) then measuring a current value of the threshold voltage; and repeating steps c) to e) until a final threshold value is obtained.

Abstract translation: 一种用于非易失性存储器的编程方法包括以下步骤：a）确定阈值电压的当前值; b）获取阈值电压的目标值; c）计算将阈值电压从当前值到目标值所需的第一数量的栅极电压脉冲; d）将第二数量的连续电压脉冲施加到所述单元的栅极端子，所述第二数量与所述第一数量相关并具有均匀增加的幅度; e）然后测量阈值电压的当前值; 并重复步骤c）至e），直到获得最终阈值。

公开(公告)号：US5805492A

公开(公告)日：1998-09-08

申请号：US722572

申请日：1996-09-27

Applicant: Danilo Gerna ,  Marco Pasotti ,  Stefano Marchese

Inventor： Danilo Gerna ,  Marco Pasotti ,  Stefano Marchese

IPC: G11C27/00 ,  G11C27/02 ,  G11C11/24 ,  G11C11/36

CPC classification number: G11C27/00 ,  G11C27/024

Abstract: The speed of a capacitive cell RAAM used for storing an optical image as electric charge is greatly enhanced by presampling the serial analog input signal on two rows or lines of presampling capacitors, each composed of the same number of capacitors as the number of columns of the capacitive cell RAAM and by "writing" in a parallel mode the selected row of said memory. The values stored in the capacitors of one of said two presampling rows are transferred (written) in the corresponding cells of the selected row of the memory while presampling continues on the other row of presampling capacitors.

Abstract translation: 用于存储光学图像作为电荷的电容单元RAAM的速度通过对两行或两行预采样电容器的串行模拟输入信号进行预取样来大大增强，每个或两行预采样电容器由相同数量的电容器组成， 电容单元RAAM，并通过所述存储器的所选行以并行模式“写入”。 存储在所述两个预采样行中的一个的电容器中的值被传送（写入）到存储器的选定行的相应单元中，同时在另一行预采样电容器上继续进行预采样。

公开(公告)号：US08264872B2

公开(公告)日：2012-09-11

申请号：US12548241

申请日：2009-08-26

Applicant: Guido De Sandre ,  Marco Pasotti

Inventor： Guido De Sandre ,  Marco Pasotti

IPC: G11C11/00 ,  G11C8/10 ,  G11C7/00

CPC classification number: G11C13/0026 ,  G11C13/0004

Abstract: A column decoder is for a phase-change memory device provided with an array of memory cells, a reading stage for reading data contained in the memory cells, and a programming stage for programming the data. The column decoder selects and enables biasing of a bitline of the array and generates a current path between the bitline and the reading stage or, alternatively, the programming stage, respectively during a reading or a programming operation of the contents of the memory cells. In the column decoder, a first decoder circuit generates a first current path between the bitline and the reading stage, and a second decoder circuit, distinct and separate from the first decoder circuit, generates a second current path, distinct from the first current path, between the bitline and the programming stage.

Abstract translation: 列解码器用于设置有存储器单元阵列的相变存储器件，用于读取存储单元中包含的数据的读取级和用于对数据进行编程的编程级。 列解码器选择并启用阵列的位线的偏置，并且在存储器单元的内容的读取或编程操作期间分别产生位线和读取级之间的电流路径，或者编程阶段。 在列解码器中，第一解码器电路在位线和读取级之间产生第一电流路径，并且与第一解码器电路不同且分离的第二解码器电路产生与第一电流路径不同的第二电流路径， 在位线和编程阶段之间。