公开(公告)号：US11836432B2

公开(公告)日：2023-12-05

申请号：US17091229

申请日：2020-11-06

Applicant: Arm Limited

Inventor： Sharath Koodali Edathil ,  Marlin Wayne Frederick, Jr.

IPC: G06F30/398 ,  G06F30/373 ,  G06F30/327 ,  G06F30/394

CPC classification number: G06F30/373 ,  G06F30/327 ,  G06F30/394 ,  G06F30/398

Abstract: Various implementations described herein refer to a method. The method may be configured to synthesize standard cells for a physical design having a power supply net with power supply rails. The method may be configured to employ a place-and-route tool so as to define edge-types for each standard cell of the standard cells in the physical design based on the power supply net and the power supply rails that touch at least one edge of each standard cell of the standard cells.

公开(公告)号：US20230385207A1

公开(公告)日：2023-11-30

申请号：US18249194

申请日：2021-08-26

Applicant: Arm Limited

Inventor： Gustavo Federico PETRI ,  Guilhem Floréal BRYANT ,  Nicholas Costas SPINALE ,  Dominic Phillip MULLIGAN

IPC: G06F13/10 ,  G06F21/44

CPC classification number: G06F13/102 ,  G06F21/44

Abstract: Examples of the present disclosure relate to an apparatus comprising interface circuitry to interface with one or more peripheral devices, processing circuitry to execute software to communicate with a given peripheral device of the one or more peripheral devices, trusted execution environment circuitry communicatively coupled to the interface circuitry and the processing circuitry. The trusted execution circuitry is configured to: receive a transmission from one of the processing circuitry and the given peripheral device to the other one of the processing circuitry and the given peripheral device; and apply a control policy in respect of the received transmission and, based on the control policy, determine whether to forward the received transmission to said other one of the processing circuitry and the given peripheral device.

公开(公告)号：US11831444B2

公开(公告)日：2023-11-28

申请号：US17310340

申请日：2020-01-09

Applicant: ARM IP LIMITED ,  ARM LIMITED

Inventor： Mikko Johannes Saarnivala ,  Szymon Sasin ,  Yongbeom Pak ,  Hannes Tschofenig ,  Kari Matias Severinkangas

IPC: H04L1/18 ,  H04L1/1829 ,  H04L67/12 ,  H04L67/141

CPC classification number: H04L1/1851 ,  H04L67/12 ,  H04L67/141

Abstract: The present techniques generally describe a machine-implemented method for configuring a retransmission timer, the method performed at the server including: receiving, from a client, a first handshake message as part of a first handshake with the client; deriving a retransmission parameter from the first handshake message; setting a first wait time of the retransmission timer based on or in response to the retransmission parameter.

公开(公告)号：US11831406B2

公开(公告)日：2023-11-28

申请号：US17000148

申请日：2020-08-21

Applicant: Arm Cloud Technology, Inc. ,  Arm Limited

Inventor： Daniil Viktorovich Egranov ,  Donald Edward Banks ,  Stuart Yoder

IPC: H04L9/00 ,  H04L9/32 ,  H04L9/08

CPC classification number: H04L9/007 ,  H04L9/0825 ,  H04L9/0894 ,  H04L9/3247

Abstract: Briefly, example methods, apparatuses, and/or articles of manufacture are disclosed that may be implemented, in whole or in part, using one or more processing devices to facilitate and/or support cryptographically associating a particular computing device with a new system owner based at least in part on a new system owner public key of a new system owner public/private key pair and a current system owner private key of a current system owner public/private key pair.

公开(公告)号：US11822815B2

公开(公告)日：2023-11-21

申请号：US17310868

申请日：2020-02-25

Applicant: Arm Limited

Inventor： Eric Ola Harald Liljedahl

IPC: G06F3/06 ,  G06F5/12

CPC classification number: G06F3/0656 ,  G06F3/0604 ,  G06F3/0631 ,  G06F3/0659 ,  G06F3/0679 ,  G06F5/12

Abstract: Ring buffer storage circuitry is disclosed which stores a ring buffer comprising multiple slots to hold a queued se-quence of data items. Data processing circuitry executes a plurality of processes to add one or more data items to be processed to the queued sequence and to remove one or more data items for process-ing from the queued sequence. Each process is arranged to perform an acquire process to acquire at least one slot in the ring buffer and to subsequently perform a release process to release the at least one slot. Ring buffer metadata storage circuitry stores metadata for the ring buffer comprising a first reference indicator and a second reference indicator. Corresponding methods and instructions are also disclosed.

公开(公告)号：US11816777B2

公开(公告)日：2023-11-14

申请号：US17680803

申请日：2022-02-25

Applicant: Arm Limited

Inventor： Maochang Dang ,  Anton Berko ,  Espen Amodt

IPC: G06T15/00 ,  G06T1/20

CPC classification number: G06T15/005 ,  G06T1/20

Abstract: There is provided a data processing system comprising a host processor and a processing resource operable to perform processing operations for applications executing on the host processor by executing commands within an appropriate command stream. The host processor is configured to generate a command stream layout indicating a sequence of commands for the command stream that is then provided to the processing resource. Some commands require sensor data. The processing resource is configured to process the sensor data into command stream data for inclusion into the command stream in order to populate the command stream for execution.

公开(公告)号：US11816227B2

公开(公告)日：2023-11-14

申请号：US16624474

申请日：2018-06-11

Applicant: ARM LIMITED

Inventor： Gareth Rhys Stockwell ,  Jason Parker ,  Djordje Kovacevic ,  Matthew Lucien Evans

IPC: G06F21/60 ,  G06F9/455 ,  G06F9/48 ,  G06F12/14 ,  G06F21/79

CPC classification number: G06F21/602 ,  G06F9/45558 ,  G06F9/4812 ,  G06F12/1491 ,  G06F21/79 ,  G06F2009/45583 ,  G06F2009/45587 ,  G06F2212/1052

Abstract: An apparatus for processing data comprises memory access circuitry to enforce ownership rights of a plurality of memory regions within a first memory. The memory access circuitry is responsive to a first export command received from a first export command source to perform a first export operation to encrypt the given owned data to form given encrypted data and to store the given encrypted data in a second memory. The memory access circuitry is responsive to a second export command for the given memory region received from a second export command source while the first export operation is being performed to determine whether said second export command source has higher priority than the first export command source and, when the second export command source has a higher priority, to interrupt the first export operation and to perform a second export operation specified by the second export command.

公开(公告)号：US20230354571A1

公开(公告)日：2023-11-02

申请号：US18012917

申请日：2021-06-23

Applicant: Arm Limited

Inventor： Rahul Mathur ,  Mudit Bhargava ,  Saurabh Pijuskumar Sinha ,  Brian Tracy Cline ,  Yew Keong Chong

IPC: H10B10/00

CPC classification number: H10B10/12

Abstract: Various implementations described herein refer to a device having a memory structure with a substrate. The device may have a signal wire buried or partially buried within at least one of the substrate and a dielectric for transmitting electrical signals. The device may be manufactured as a memory device having a memory cell structure with the signal wire buried or partially buried in the substrate.

公开(公告)号：US20230325194A1

公开(公告)日：2023-10-12

申请号：US18042845

申请日：2021-08-26

Applicant: ARM LIMITED

Inventor： Syed Ali Mustafa ZAIDI ,  Giacomo GABRIELLI

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/3851 ,  G06F9/3016

Abstract: A data processing apparatus and a method for processing data are disclosed. The data processing apparatus comprises: multithreaded processing circuitry to perform processing operations of a plurality of micro-threads, each micro-thread operating in a corresponding execution context defining an architectural state. Thread control circuitry collects runtime data indicative of a performance metric relating to the processing operations. Decoder circuitry is responsive to a detach instruction in a first micro-thread of instructions executed in a first execution context defining a first architectural state, the detach instruction specifying an address, to provide detach control signals to the thread control circuitry. When the runtime data meet a parallelisation criterion, the thread control circuitry is responsive to the detach control signals to spawn a second micro-thread of instructions executed in a second execution context defining a second architectural state based on the first architectural state, the second micro-thread of instructions comprising a subset of instructions of the first micro-thread of instructions starting at the address.

公开(公告)号：US20230317717A1

公开(公告)日：2023-10-05

申请号：US17708915

申请日：2022-03-30

Applicant: Arm Limited

Inventor： Amit Chhabra ,  Brian Tracy Cline ,  David Victor Pietromonaco

IPC: H01L27/06 ,  H01L27/092 ,  H01L29/423 ,  H01L29/06 ,  H03K19/20 ,  G11C11/412

CPC classification number: H01L27/0688 ,  H01L27/092 ,  H01L29/42392 ,  H01L29/0665 ,  H03K19/20 ,  G11C11/412

Abstract: Various implementations described herein are related to a device having a multi-device stack structure for use in multi-layered circuit architectures. The multi-device stack structure may have P-type transistors and N-type transistors that are arranged vertically in a multi-transistor stack configuration. In some implementations, the device may have a multi-device stack structure for use in multi-bit memory and/or logic architecture that is formed with complementary field effect transistor (CFET) technology.