公开(公告)号：US20080116516A1

公开(公告)日：2008-05-22

申请号：US11674157

申请日：2007-02-13

Applicant: Yeong-Feng Wang ,  Chih-Jui Pan ,  Liang-Bin Yu

Inventor： Yeong-Feng Wang ,  Chih-Jui Pan ,  Liang-Bin Yu

IPC: H01L31/0392 ,  H01L21/70

CPC classification number: H01L27/124 ,  G02F1/136213 ,  H01L27/1255 ,  H01L29/78642

Abstract: A TFT array substrate is provided. The TFT array substrate includes a substrate, a patterned first metallic layer, a patterned semiconductor layer, a patterned transparent conductive layer, a patterned dielectric layer, and a patterned second metallic layer. Elements of each TFT of the TFT array substrate are arranged vertically, so that the TFT array substrate has relatively small fabrication area and is operable with a high conducting current. Further, the storage capacitance can be enhanced by enclosing or sandwiching the transparent electrodes with the common lines and the second metallic layer, or alternatively by enclosing or sandwiching the second metallic layer with the common lines and the transparent electrodes.

Abstract translation: 提供TFT阵列基板。 TFT阵列基板包括基板，图案化第一金属层，图案化半导体层，图案化透明导电层，图案化电介质层和图案化的第二金属层。 TFT阵列基板的每个TFT的元件垂直布置，使得TFT阵列基板具有相对较小的制造面积并且可以以高导通电流工作。 此外，通过用公共线和第二金属层包围或夹着透明电极，或者通过用公共线和透明电极包围或夹持第二金属层，可以增强存储电容。

公开(公告)号：US20070258035A1

公开(公告)日：2007-11-08

申请号：US11566724

申请日：2006-12-05

Applicant: Yeong-Feng Wang ,  Liang-Bin Yu ,  Chih-Jui Pan

Inventor： Yeong-Feng Wang ,  Liang-Bin Yu ,  Chih-Jui Pan

IPC: G02F1/13

CPC classification number: G02F1/136286 ,  G02F2001/13606 ,  G02F2001/13629 ,  G02F2001/136295 ,  G02F2201/40

Abstract: A liquid crystal display (LCD) array substrate and its manufacturing method are provided. Scan lines and data lines of the LCD array substrate are composed of two conductive layers to decrease their RC delay. Moreover, the dielectric layer and even the planarization layer are removed from pixel areas defined by the scan lines and the data lines to increase the light penetration percentage.

Abstract translation: 提供液晶显示（LCD）阵列基板及其制造方法。 LCD阵列基板的扫描线和数据线由两个导电层组成，以减少它们的RC延迟。 此外，从由扫描线和数据线限定的像素区域中去除介电层甚至平坦化层以增加光线穿透率。

公开(公告)号：US07279735B1

公开(公告)日：2007-10-09

申请号：US10838215

申请日：2004-05-05

Applicant: Bin Yu ,  Haihong Wang

Inventor： Bin Yu ,  Haihong Wang

IPC: H01L29/788

CPC classification number: H01L29/7883 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/785

Abstract: A non-volatile memory device includes a substrate, an insulating layer, a fin structure, a floating gate, an inter-gate dielectric and a control gate. The insulating layer is formed on the substrate and the fin structure is formed on the insulating layer. The fin structure may include a strained layer formed on a non-strained layer.

Abstract translation: 非易失性存储器件包括衬底，绝缘层，翅片结构，浮动栅极，栅极间电介质和控制栅极。 绝缘层形成在基板上，翅片结构形成在绝缘层上。 翅片结构可以包括形成在非应变层上的应变层。

公开(公告)号：US20070153194A1

公开(公告)日：2007-07-05

申请号：US11563718

申请日：2006-11-28

Applicant: Yeong-Feng Wang ,  Chun-Hao Tung ,  Liang-Bin Yu

Inventor： Yeong-Feng Wang ,  Chun-Hao Tung ,  Liang-Bin Yu

IPC: G02F1/1343

CPC classification number: G02F1/136213 ,  G02F2001/13606

Abstract: A pixel unit comprising a first metal layer and a second metal layer. The first metal layer comprises a gate electrode and a first electrode. The second metal layer comprises a drain electrode, a source electrode, and a second electrode. The drain electrode overlaps the gate electrode in a first overlapping region. The source electrode overlaps the gate electrode in a second overlapping region. The second electrode overlaps the first electrode in a third overlapping region. The size of the first electrode approximates that of the second electrode. The first electrode and the second electrode are staggered.

Abstract translation: 一种像素单元，包括第一金属层和第二金属层。 第一金属层包括栅电极和第一电极。 第二金属层包括漏电极，源电极和第二电极。 漏电极在第一重叠区域与栅电极重叠。 源电极在第二重叠区域与栅电极重叠。 第二电极在第三重叠区域与第一电极重叠。 第一电极的尺寸近似于第二电极的尺寸。 第一电极和第二电极交错。

公开(公告)号：US20070118868A1

公开(公告)日：2007-05-24

申请号：US11286651

申请日：2005-11-23

Applicant: Cha Zhang ,  Bin Yu ,  Yong Rui

Inventor： Cha Zhang ,  Bin Yu ,  Yong Rui

IPC: H04N7/173

CPC classification number: H04N7/181 ,  H04N21/4223 ,  H04N21/4316

Abstract: A computer network-based distributed presentation system and process is presented that controls the display of one or more video streams output by multiple video cameras located across multiple presentation sites on display screens located at each presentation site. The distributed presentation system and process provides the ability for a user at a site to customize the screen configuration (i.e., what video streams are display at any one time and in what format) for that site via a two-layer display director module. In the design layer of the module, a user interface is provided for a user to specify display priorities dictating what video streams are to be displayed on the screen over time. These display priorities are then provided to the execution layer of the module which translates them into probabilistic timed automata and uses the automata to control what is displayed on the display screen.

Abstract translation: 提出了一种基于计算机网络的分布式呈现系统和过程，其控制由位于每个呈现站点的显示屏幕上的多个呈现站点上的多个摄像机输出的一个或多个视频流的显示。 分布式呈现系统和过程提供了一个站点用户通过两层显示导演模块定制屏幕配置（即，任何一个时间和以什么格式显示什么视频流）的能力。 在模块的设计层中，为用户提供用户界面，以指定显示优先级，指定在屏幕上随时间显示哪些视频流。 然后将这些显示优先级提供给模块的执行层，将其转换为概率定时自动机，并使用自动机来控制显示屏上显示的内容。

公开(公告)号：US07196372B1

公开(公告)日：2007-03-27

申请号：US10614177

申请日：2003-07-08

Applicant: Bin Yu ,  Ming-Ren Lin ,  Srikanteswara Dakshina-Murthy ,  Zoran Krivokapic

Inventor： Bin Yu ,  Ming-Ren Lin ,  Srikanteswara Dakshina-Murthy ,  Zoran Krivokapic

IPC: H01L29/788

CPC classification number: H01L29/7887 ,  H01L21/28273 ,  H01L27/11568 ,  H01L29/785

Abstract: A non-volatile memory device includes a substrate, an insulating layer, a fin, an oxide layer, spacers and one or more control gates. The insulating layer is formed on the substrate and the fin is formed on the insulating layer. The oxide layer is formed on the fin and acts as a tunnel oxide for the memory device. The spacers are formed adjacent the side surfaces of the fin and the control gates are formed adjacent the spacers. The spacers act as floating gate electrodes for the non-volatile memory device.

Abstract translation: 非易失性存储器件包括衬底，绝缘层，鳍，氧化物层，间隔物和一个或多个控制栅极。 绝缘层形成在基板上，并且鳍形成在绝缘层上。 氧化层形成在翅片上并用作存储器件的隧道氧化物。 间隔件邻近翅片的侧表面形成，并且控制栅极邻近间隔件形成。 间隔件用作非易失性存储器件的浮栅电极。

公开(公告)号：US07125776B2

公开(公告)日：2006-10-24

申请号：US11030191

申请日：2005-01-07

Applicant: Krishnashree Achuthan ,  Shibly S. Ahmed ,  Haihong Wang ,  Bin Yu

Inventor： Krishnashree Achuthan ,  Shibly S. Ahmed ,  Haihong Wang ,  Bin Yu

IPC: H01L21/336 ,  H01L21/00 ,  H01L21/84

CPC classification number: H01L29/785 ,  C09G1/02 ,  H01L21/31053 ,  H01L21/3212 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66795 ,  H01L29/6681 ,  Y10S438/959

Abstract: A method of manufacturing a MOSFET type semiconductor device includes planarizing a gate material layer that is deposited over a channel. The planarization is performed in a multi-step process that includes an initial “rough” planarization and then a “fine” planarization. The slurry used for the finer planarization may include added material that tends to adhere to low areas of the gate material.

Abstract translation: 制造MOSFET型半导体器件的方法包括平坦化沉积在沟道上的栅极材料层。 平面化在包括初始“粗糙”平坦化然后是“精细”平坦化的多步骤过程中进行。 用于更精细平坦化的浆料可以包括倾向于粘附到栅极材料的低区域的添加材料。

公开(公告)号：US07091097B1

公开(公告)日：2006-08-15

申请号：US10933424

申请日：2004-09-03

Applicant: Eric N. Paton ,  Qi Xiang ,  Cyrus E. Tabery ,  Bin Yu ,  Robert B. Ogle

Inventor： Eric N. Paton ,  Qi Xiang ,  Cyrus E. Tabery ,  Bin Yu ,  Robert B. Ogle

IPC: H01L21/336

CPC classification number: H01L21/268 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/2658 ,  H01L29/6659 ,  H01L29/7833

Abstract: A method of fabricating a semiconductor device comprises forming a gate electrode over a substrate and forming deep amorphous regions within the substrate. And implanting dopants to form deep source/drain regions at a depth less than that of the deep amorphous regions, partially re-crystallizing portions of the deep amorphous regions to reduce their depth, and re-crystallizing the reduced amorphous regions to form activated final source/drain regions.

Abstract translation: 制造半导体器件的方法包括在衬底上形成栅电极并在衬底内形成深非晶区域。 并且注入掺杂剂以在深非晶区域的深度处形成深的源极/漏极区域，部分地重新结晶深非晶区域的部分以减小它们的深度，并且将还原的非晶区域再结晶以形成激活的最终光源 /漏区。

公开(公告)号：US07084018B1

公开(公告)日：2006-08-01

申请号：US10838228

申请日：2004-05-05

Applicant: Shibly S. Ahmed ,  Bin Yu

Inventor： Shibly S. Ahmed ,  Bin Yu

IPC: H01L21/84

CPC classification number: H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: A method of reducing buried oxide undercut during FinFET formation includes forming a fin on a buried oxide layer and forming a source region adjacent a first end of the fin and a drain region adjacent a second end of the fin. The method further includes forming a sacrificial oxide layer over the fin and source and drain regions and forming a gate over the fin, wherein the sacrificial oxide layer reduces undercutting of the buried oxide layer during gate formation.

Abstract translation: 在FinFET形成期间减少掩埋氧化物底切的方法包括在掩埋氧化物层上形成翅片并形成与鳍片的第一端相邻的源极区域和与鳍片的第二端部相邻的漏极区域。 该方法还包括在鳍片和源极和漏极区域上形成牺牲氧化物层并在鳍片上形成栅极，其中牺牲氧化物层在栅极形成期间减少掩埋氧化物层的底切。

公开(公告)号：US20060145600A1

公开(公告)日：2006-07-06

申请号：US11205408

申请日：2005-08-16

Applicant: Liang-Bin Yu ,  Tien-Shou Shieh ,  Hui-Lung Kuo ,  Mei-Rurng Tseng ,  Pin-Sien Yu

Inventor： Liang-Bin Yu ,  Tien-Shou Shieh ,  Hui-Lung Kuo ,  Mei-Rurng Tseng ,  Pin-Sien Yu

IPC: H05B33/14 ,  H05B33/22

CPC classification number: H01L51/5281

Abstract: An organic light emitting diode (OLED) with a brightness enhancer. The OLED comprises a substrate having a first surface and a second surface oppositely. An anode electrode is disposed on the first surface of the substrate. An organic light emitting layer is disposed on the anode electrode. A cathode electrode is disposed on the organic light emitting layer. A brightness enhancer is disposed on the second surface of the substrate.

Abstract translation: 具有亮度增强器的有机发光二极管（OLED）。 OLED包括具有相对的第一表面和第二表面的基底。 阳极电极设置在基板的第一表面上。 有机发光层设置在阳极电极上。 阴极电极设置在有机发光层上。 亮度增强器设置在基板的第二表面上。