Storage Protocol Emulation in a Peripheral Device

    公开(公告)号:US20220309019A1

    公开(公告)日:2022-09-29

    申请号:US17211928

    申请日:2021-03-25

    Abstract: A peripheral device includes a host interface and processing circuitry. The host interface is configured to communicate with a host over a peripheral bus. The processing circuitry is configured to expose on the peripheral bus a peripheral-bus device that communicates with the host using a bus storage protocol, to receive, using the exposed peripheral-bus device, Input/Output (I/O) transactions that are issued by the host, and to complete the I/O transactions for the host in accordance with a network storage protocol, by running at least part of a host-side protocol stack of the network storage protocol.

    OPTICAL INTERPOSERS
    153.
    发明申请

    公开(公告)号:US20220276455A1

    公开(公告)日:2022-09-01

    申请号:US17631655

    申请日:2019-08-21

    Abstract: Apparatuses, systems, and associated methods of manufacturing are described that provide an optical interposer and associated communication system. An example optical interposer includes a substrate having a first end that receives a first optical fiber welded thereto and a second end that receives a plurality of photonic integrated circuits (PICs) attached thereto. The interposer further includes an optical waveguide network defined by the substrate that provides optical communication between the first welded optical fiber and the plurality of PICs. The optical waveguide network also includes optical redistribution elements supported by the substrate. In an operational configuration, the optical interposer receives a first input optical signal from the first welded optical fiber, and the plurality of optical redistribution elements successively split the first input optical signal such that a plurality of output optical signals is directed to the plurality of PICs.

    Efficient Montgomery Multiplier
    154.
    发明申请

    公开(公告)号:US20220269487A1

    公开(公告)日:2022-08-25

    申请号:US17180993

    申请日:2021-02-22

    Abstract: An Integrated Montgomery Calculation Engine (IMCE), for multiplying two multiplicands modulo a predefined number, includes a Carry Save Adder (CSA) circuit and control circuitry. The CSA circuit has multiple inputs, and has outputs including a sum output and a carry output. The control circuitry is coupled to the inputs and the outputs of the CSA circuit and is configured to operate the CSA circuit in at least (i) a first setting that calculates a Montgomery precompute value and (ii) a second setting that calculates a Montgomery multiplication of the two multiplicands.

    Efficient parsing tuned to prevalent packet types

    公开(公告)号:US11425230B2

    公开(公告)日:2022-08-23

    申请号:US17160407

    申请日:2021-01-28

    Abstract: A parsing apparatus includes an interface, a first parser, a second parser and a controller. The interface is configured to receive packets belonging to a plurality of predefined packet types. The first parser is configured to identify any of the packet types. The second parser is configured to identify only a partial subset of the packet types. The controller is configured to receive a packet via the interface, to attempt identifying a packet type of the received packet using the second parser, and in response to detecting that identifying the packet type using the second parser fails, to revert to identify the packet type of the received packet using the first parser.

    Transparent failover in a network interface controller

    公开(公告)号:US11336508B2

    公开(公告)日:2022-05-17

    申请号:US16024864

    申请日:2018-07-01

    Abstract: A network interface apparatus includes a host interface for connection to a host processor and a network interface, which includes multiple distinct physical ports. Processing circuitry associates each of a plurality of virtual entities running on the host processor with a respective one of the physical ports, so that while both of the first and second physical ports are operational, the processing circuitry transmits data packets on behalf of first and second virtual entities, using assigned upper-layer addresses, through associated first and second physical ports. In response to an indication that the first physical port has ceased to operate, the processing circuitry transmits the data packets on behalf of the first virtual entity through the second physical port without changing the upper-layer addresses.

    METHOD AND APPARATUS FOR SYMBOL-ERROR-RATE (SER) BASED TUNING OF TRANSMITTERS AND RECEIVERS

    公开(公告)号:US20220116125A1

    公开(公告)日:2022-04-14

    申请号:US17068442

    申请日:2020-10-12

    Abstract: Embodiments are disclosed for a sequence selective symbol checker for communication systems. An example method includes configuring a symbol checker of a receiver with first binary sequence data generated by a symbol generator of the receiver. The example method also includes comparing, using the symbol checker, second binary sequence data provided by a transmitter to the first binary sequence data to generate error count data related to a number of errors for symbols associated with the second binary sequence data. The example method also includes determining total count data related to a number of symbols associated with the first binary sequence data. The example method also includes determining error ratio data associated with the transmitter based on the error count data and the total count data.

    Method and apparatus for symbol-error-rate (SER) based tuning of transmitters and receivers

    公开(公告)号:US11303363B1

    公开(公告)日:2022-04-12

    申请号:US17068442

    申请日:2020-10-12

    Abstract: Embodiments are disclosed for a sequence selective symbol checker for communication systems. An example method includes configuring a symbol checker of a receiver with first binary sequence data generated by a symbol generator of the receiver. The example method also includes comparing, using the symbol checker, second binary sequence data provided by a transmitter to the first binary sequence data to generate error count data related to a number of errors for symbols associated with the second binary sequence data. The example method also includes determining total count data related to a number of symbols associated with the first binary sequence data. The example method also includes determining error ratio data associated with the transmitter based on the error count data and the total count data.

    OPTICAL COUPLER
    160.
    发明申请

    公开(公告)号:US20220099891A1

    公开(公告)日:2022-03-31

    申请号:US17421004

    申请日:2020-01-02

    Abstract: An optical interconnect device and the method of fabricating it are described. The device includes an in-plane laser cavity transmitting a light beam along a first direction, a Franz Keldysh (FK) optical modulator transmitting the light beam along the first direction, a mode-transfer module including a tapered structure disposed after the FK optical modulator along the first direction to enlarge the spot size of the light beam to match an external optical fiber and a universal coupler controlling the light direction. The tapered structure can be made linear or non-linear along the first direction. The universal coupler passes the laser light to an in-plane external optical fiber if the fiber is placed along the first direction, or it is a vertical coupler in the case that the external optical fiber is placed perpendicularly to the substrate surface. The coupler is coated with highly reflective material.

Patent Agency Ranking