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公开(公告)号：US20230288203A1
公开(公告)日：2023-09-14
申请号：US18169438
申请日：2023-02-15
Inventor： SHOTA HARADA , KEITARO ITO , HIDEAKI NISHIKAWA , YUUKI INAGAKI , KATSUAKI GOTO , TAKAHIKO YOSHIDA , YUSUKE KAWAI
IPC: G01C19/5712
CPC classification number: G01C19/5712
Abstract: In a mounting structure, a micro vibrator has: a curved surface portion having a hemispherical curved surface; a connecting portion extending from the curved surface portion toward a center of a hemispherical shape of the curved surface portion; and a surface electrode covering at least a part of the connecting portion and at least a part of the curved surface portion. A mounting substrate has two or more wirings and a part of the micro vibrator is connected to the mounting substrate. The wirings each have an electrode connection portion connected to a portion of the surface electrode covering the connecting portion at an end. The two or more wirings include a voltage application wiring and a voltage detection wiring. The voltage application wiring is spaced away from the voltage detection wiring on the mounting substrate.
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公开(公告)号：US11757009B2
公开(公告)日：2023-09-12
申请号：US17398060
申请日：2021-08-10
Inventor： Hiroki Miyake
IPC: H01L29/36 , H01L29/24 , H01L21/425 , H01L29/78 , H01L29/872 , H01L29/861
CPC classification number: H01L29/36 , H01L21/425 , H01L29/24 , H01L29/7813 , H01L29/8613 , H01L29/872
Abstract: A semiconductor device includes: a first semiconductor layer having an N conductive type and made of a gallium oxide-based semiconductor; and a second semiconductor layer made of a gallium oxide-based semiconductor, in contact with the first semiconductor layer, and having the N conductive type with an electrically active donor concentration higher than an electrically active donor concentration of the first semiconductor layer. A difference between a donor concentration of the first semiconductor layer and a donor concentration of the second semiconductor layer is smaller than a difference between the electrically active donor concentration of the first semiconductor layer and the electrically active donor concentration of the second semiconductor layer.
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公开(公告)号：US11740087B2
公开(公告)日：2023-08-29
申请号：US17703164
申请日：2022-03-24
Inventor： Shota Harada , Keitaro Ito , Katsuaki Goto , Yuuki Inagaki , Takahiko Yoshida , Yusuke Kawai , Teruhisa Akashi , Hirofumi Funabashi
Abstract: A micro vibration body includes a curved surface portion, a recessed portion recessed from the curved surface portion, a bottom surface protruding portion protruding from a bottom surface of the recessed portion, and a through hole in the bottom surface protruding portion. A mounting substrate has a positioning recess, into which the bottom surface protruding portion is inserted, and electrode portions surrounding the inner frame portion. A joining member is in the positioning recess and joins the bottom surface protruding portion with the mounting substrate. The bottom surface is in contact with a region of the mounting substrate around the positioning recess. The bottom surface protruding portion has a tip end surface that is at a distance from the positioning recess. The joining member at least partially enters the through hole and is electrically connected to the conductive layer.
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公开(公告)号：US20230268185A1
公开(公告)日：2023-08-24
申请号：US18156682
申请日：2023-01-19
Inventor： Hiroyuki TAKAHATA , Yuji NAGUMO , Masashi UECHA
IPC: H01L21/304 , H01L21/683
CPC classification number: H01L21/304 , H01L21/6836 , H01L2221/68327 , H01L2221/6834
Abstract: A manufacturing method of a semiconductor device, includes: preparing a wafer having a first surface on which a plurality of semiconductor elements is formed and to which a support plate is attached through an adhesive; grinding a second surface of the wafer opposite to the first surface in a state where the support plate is attached to the first surface of the wafer; forming a vertical crack inside the wafer and along a boundary between the adjacent semiconductor elements by pressing a scribe wheel against the wafer along the boundary; separating the support plate from the wafer while leaving the adhesive on the first surface of the wafer; cleaving the wafer along the boundary by pressing a breaking bar against the wafer over the adhesive and along the boundary; and removing the adhesive from at least one of the semiconductor elements divided from the wafer by the cleaving.
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公开(公告)号：US20230178170A1
公开(公告)日：2023-06-08
申请号：US17898576
申请日：2022-08-30
Inventor： TETSURO TAKIZAWA
CPC classification number: G11C29/52 , G11C29/783 , G11C29/20
Abstract: A semiconductor memory device includes: a plurality of banks having a data storage unit and an error correction code storage unit; an error correction code generation unit; an error correction unit; a low counter that determines a low address as a refresh target; a bank counter that determines a bank address as an error correction target; and a column counter that determines a column address as the error correction target. The error correction unit performs the error correction process on a data of an error correction target address determined based on the low counter, the bank counter, and the column counter when receiving a refresh command.
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Patent Agency Ranking
公开(公告)号：US20230170399A1
公开(公告)日：2023-06-01
申请号：US18054568
申请日：2022-11-11
Inventor： YOSUKE MAEGAWA , YOHEI IWAHASHI
CPC classification number: H01L29/66068 , H01L21/0475 , H01L29/7813
Abstract: A method for manufacturing a semiconductor device includes: preparing a semiconductor substrate; arranging a mask on one surface of the semiconductor substrate; forming opening portions in the mask by patterning so as to expose planned formation regions of the semiconductor substrate where trenches are to be formed; forming the trenches, which extend in a longitudinal direction along a planar direction of the semiconductor substrate, in the semiconductor substrate adjacent to the one surface, by performing a first etching using the mask; forming a rounded portion at an opening end portion of each of the trenches by performing a second etching in a state where the mask is arranged and under a condition that a selectivity of the mask is higher than that of the semiconductor substrate; and arranging a gate insulating film and a gate electrode in each of the trenches, thereby to form trench gate structures.
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公开(公告)号：US20230154987A1
公开(公告)日：2023-05-18
申请号：US17981049
申请日：2022-11-04
Inventor： HIROKI TSUMA , YUJI NAGUMO , MASASHI UECHA , TERUAKI KUMAZAWA
CPC classification number: H01L29/1608 , H01L29/04 , H01L21/02008 , H01L21/02447 , H01L21/02529 , H01L21/02598
Abstract: A silicon carbide semiconductor device includes a silicon carbide semiconductor layer and a side silicide layer. The silicon carbide semiconductor layer includes a silicon carbide single crystal and has a main surface, a rear surface opposite to the main surface, and a side surface connecting the main surface and the rear surface and formed by a cleavage plane. The silicon carbide semiconductor layer further includes a modified layer. The modified layer forms a part of the side surface located close to the rear surface and has an atomic arrangement structure of silicon carbide different from an atomic arrangement structure of the silicon carbide single crystal. The side silicide layer includes a metal silicide that is a compound of a metal element and silicon. The side silicide layer is disposed on the side surface of the silicon carbide semiconductor layer and is adjacent to the modified layer.
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公开(公告)号：US20230126560A1
公开(公告)日：2023-04-27
申请号：US17968877
申请日：2022-10-19
Inventor： SOYA TANIGUCHI , YOSHIKAZU FURUTA , KAZUO MATSUKAWA , YOSHIYUKI UTAGAWA
IPC: G01R31/396 , H01M10/42 , G01R31/382 , H03K21/40
Abstract: A battery monitoring system includes a battery monitoring ECU and battery monitoring devices which are sequentially connected in a connection configuration. The battery monitoring ECU includes a clock generator that generates a first clock signal. Each battery monitoring device includes a second clock generator that generates a second clock signal, a controller that causes a frequency correction block to correct a frequency of the second clock signal in line with the first clock signal and causes the battery monitor to monitor a battery cell using the second clock signal that has been corrected, and a switch that, according to an instruction of the battery monitoring ECU, switches a circuit configuration to a state in which a signal received from a preceding device is transmitted to a succeeding device in the connection configuration.
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公开(公告)号：US20230126107A1
公开(公告)日：2023-04-27
申请号：US17884871
申请日：2022-08-10
Inventor： Shotaro WADA , Tomohiro NEZUKA
Abstract: A clock signal generation circuit for a switched capacitor circuit with a chopping function unit includes: first and second synchronous clock circuits that generate first and second synchronous clock signals, respectively; an edge signal generation circuit that generates one or more rise and fall edge signals by delaying the first synchronous clock signal; a first clock generator that generate a first clock signal group for driving the switched capacitor circuit; and a second clock generator that generates a second clock signal group for driving the chopping function unit. Frequencies of the first and second clock signal groups are respectively defined by the first and second synchronous clock circuits. Rise and fall edges of the first and second clock signal groups are defined by the edge signal generation circuit.
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公开(公告)号：US20230114152A1
公开(公告)日：2023-04-13
申请号：US17953456
申请日：2022-09-27
Inventor： HIRONORI AKIYAMA , AKIMASA NIWA
IPC: H03K17/687 , H03K17/284 , H03K17/16 , H03K17/06 , H03K17/94
Abstract: A gate drive device drives a gate of a semiconductor switching element and controls a transient voltage corresponding to a voltage of a main terminal of the semiconductor switching element to a target value of the transient voltage at a time of switching the semiconductor switching element. The gate drive device includes a calculation circuit, a drive circuit, a detection circuit, and a learning circuit. The calculation circuit executes a predetermined calculation mode to calculate an operation amount for operating gate drive speed of the semiconductor switching element. The drive circuit drives the gate of the semiconductor switching element according to the operation amount. The detection circuit detects the transient voltage. The learning circuit executes learning processing to change the predetermined calculation mode based on the operation amount calculated by the calculation circuit and the transient voltage detected by the detection circuit.
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