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    Microelectronic devices, related electronic systems, and methods of forming microelectronic devices
    153.
    发明授权
    Microelectronic devices, related electronic systems, and methods of forming microelectronic devices 有权

    公开(公告)号：US11587919B2

    公开(公告)日：2023-02-21

    申请号：US16932098

    申请日：2020-07-17

    Applicant: Micron Technology, Inc.

    Inventor： Aaron S. Yip ,  Kunal R. Parekh ,  Akira Goda

    IPC: H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H01L25/00

    Abstract: A microelectronic device comprises a first die comprising a memory array region comprising a stack structure comprising vertically alternating conductive structures and insulative structures, and vertically extending strings of memory cells within the stack structure. The first die further comprises first control logic region comprising a first control logic devices including at least a word line driver. The microelectronic device further comprise a second die attached to the first die, the second die comprising a second control logic region comprising second control logic devices including at least one page buffer device configured to effectuate a portion of control operations of the vertically extending string of memory cells. Related microelectronic devices, electronic systems, and methods are also described.

    Transistors including oxide semiconductive materials, and related microelectronic devices, memory devices, electronic systems, and methods
    154.
    发明授权
    Transistors including oxide semiconductive materials, and related microelectronic devices, memory devices, electronic systems, and methods 有权

    公开(公告)号：US11430895B2

    公开(公告)日：2022-08-30

    申请号：US16891462

    申请日：2020-06-03

    Applicant: Micron Technology, Inc.

    Inventor： Kamal M. Karda ,  Guangyu Huang ,  Haitao Liu ,  Akira Goda

    IPC: H01L29/786 ,  H01L27/11529 ,  H01L27/11573 ,  H01L29/66

    Abstract: A transistor comprises a lower contact structure, a channel structure, a dielectric fill structure, and an upper contact structure. The lower contact structure comprises a first oxide semiconductive material. The channel structure contacts the lower contact structure and comprises a second oxide semiconductive material having a smaller atomic concentration of one or more metals than the first oxide semiconductive material. The dielectric fill structure contacts an inner side surface of the channel structure and has a recessed upper surface relative to the channel structure. The upper contact structure comprises a third oxide semiconductive material having a greater atomic concentration of the one or more metals than the channel structure. The upper contact structure comprises a first portion contacting the upper surface of the dielectric fill structure and the inner side surface of the channel structure, and a second portion contacting the upper surface of the channel structure.

    Separate partition for buffer and snapshot memory
    155.
    发明授权
    Separate partition for buffer and snapshot memory 有权

    公开(公告)号：US11385819B2

    公开(公告)日：2022-07-12

    申请号：US16995682

    申请日：2020-08-17

    Applicant: Micron Technology, Inc.

    Inventor： Kishore K. Muchherla ,  Niccolo' Righetti ,  Jeffrey S. McNeil, Jr. ,  Akira Goda ,  Todd A. Marquart ,  Mark A. Helm ,  Gil Golov ,  Jeremy Binfet ,  Carmine Miccoli ,  Giuseppina Puzzilli

    IPC: G06F3/06

    Abstract: A system includes a processing device and trigger circuitry to signal the processing device responsive, at least in part, based on a determination that a trigger event has occurred. The system can further include a memory device communicatively coupled to the processing device. The memory device can include a cyclic buffer partition portion having a first endurance characteristic and a first reliability characteristic associated therewith. The memory device can further include a snapshot partition portion coupled to the cyclic buffer partition portion via hold-up capacitors. The snapshot partition portion can have a second endurance characteristic and a second reliability characteristic associated therewith. The processing device can perform operations including writing received data sequentially to the cyclic buffer partition portion and writing, based at least in part on the determination that the trigger event has occurred, data from the cyclic buffer partition portion to the snapshot partition portion.

    METHODS OF FORMING MICROELECTRONIC DEVICES, AND RELATED MICROELECTRONIC DEVICES AND ELECTRONIC SYSTEMS
    157.
    发明申请
    METHODS OF FORMING MICROELECTRONIC DEVICES, AND RELATED MICROELECTRONIC DEVICES AND ELECTRONIC SYSTEMS 有权

    公开(公告)号：US20220149015A1

    公开(公告)日：2022-05-12

    申请号：US17649022

    申请日：2022-01-26

    Applicant: Micron Technology, Inc.

    Inventor： Kunal R. Parekh ,  Paolo Tessariol ,  Akira Goda

    IPC: H01L25/065 ,  H01L23/48 ,  H01L23/00 ,  H01L25/00 ,  H01L21/768 ,  H01L23/482

    Abstract: A microelectronic device comprises a memory array region, a control logic region, and an additional control logic region. The memory array region comprises a stack structure comprising vertically alternating conductive structures and insulating structures, and vertically extending strings of memory cells within the stack structure. The control logic region underlies the stack structure and comprises control logic devices configured to effectuate a portion of control operations for the vertically extending strings of memory cells. The additional control logic region overlies the stack structure and comprises additional control logic devices configured to effectuate an additional portion of the control operations for the vertically extending strings of memory cells. Methods of forming a microelectronic device, and additional microelectronic devices and electronic systems are also described.

    Multi-decks memory device including inter-deck switches
    160.
    发明授权
    Multi-decks memory device including inter-deck switches 有权

    公开(公告)号：US11289163B2

    公开(公告)日：2022-03-29

    申请号：US17087166

    申请日：2020-11-02

    Applicant: Micron Technology, Inc.

    Inventor： Benben Li ,  Akira Goda ,  Ramey M. Abdelrahaman ,  Ian C. Laboriante ,  Krishna K. Parat

    IPC: G11C16/04 ,  H01L27/11558 ,  H01L27/11524 ,  H01L45/00 ,  G11C11/408 ,  H01L27/24 ,  H01L27/11597 ,  G11C8/08 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/1157

    Abstract: Some embodiments include apparatuses and methods of forming such apparatuses. One of the apparatus includes first memory cells located in different levels in a first portion of the apparatus, second memory cells located in different levels in a second portion of the apparatus, a switch located in a third portion of the apparatus between the first and second portions, first and second control gates to access the first and second memory cells, an additional control gate located between the first and second control gates to control the switch, a first conductive structure having a thickness and extending perpendicular to the levels in the first portion of the apparatus, a first dielectric structure between the first conductive structure and charge-storage portions of the first memory cells, a second dielectric structure having a second thickness between the second conductive structure and a sidewall of the additional control gate, the second thickness being greater than the first thickness.

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