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    APPARATUSES AND METHODS FOR WRITE DATA PRECONDITIONING USING A NEURAL NETWORK
    151.
    发明申请
    APPARATUSES AND METHODS FOR WRITE DATA PRECONDITIONING USING A NEURAL NETWORK 有权

    公开(公告)号：US20240412796A1

    公开(公告)日：2024-12-12

    申请号：US18734766

    申请日：2024-06-05

    Applicant: Micron Technology, Inc.

    Inventor： Fa-Long Luo ,  Jaime Cummins

    IPC: G11C29/12 ,  G11C11/54 ,  G11C29/36

    Abstract: A memory includes a receiver circuit configured to receive write data via a data terminal, and a neural network based preconditioning circuit configured to receive a write data signal according to the write data. A neural network of the preconditioning circuit is configured to precondition the write data signal based on a characteristic of a write data path to provide a modified write data signal. The memory further includes a memory array configured to store the write data based on the modified write data signal.

    DETERMINING CHANNEL CHARACTERISTICS SYSTEMS AND METHODS
    153.
    发明申请
    DETERMINING CHANNEL CHARACTERISTICS SYSTEMS AND METHODS 有权

    公开(公告)号：US20240385977A1

    公开(公告)日：2024-11-21

    申请号：US18666457

    申请日：2024-05-16

    Applicant: Micron Technology, Inc.

    Inventor： Fa-Long Luo ,  Jaime Cummins

    IPC: G06F13/16 ,  H04L5/00

    Abstract: Apparatuses and methods for determining a channel characteristic are disclosed. The channel characteristic can be a characteristic of a channel between a memory controller and a memory. The channel characteristic is determined at the memory controller relating to logic levels of data written to or read from the memory over the channel, and transceiver settings of a transceiver of the memory controller are modified according to the determined characteristic. The channel characteristic can be determined based on storing a pilot signal at the memory controller, causing the pilot signal to be written to the memory, and comparing a read pilot signal corresponding to the written pilot signal with the stored pilot signal.

    COOPERATIVE LEARNING NEURAL NETWORKS AND SYSTEMS
    155.
    发明公开
    COOPERATIVE LEARNING NEURAL NETWORKS AND SYSTEMS 审中-公开

    公开(公告)号：US20240256869A1

    公开(公告)日：2024-08-01

    申请号：US18609221

    申请日：2024-03-19

    Applicant: Micron Technology, Inc.

    Inventor： Fa-Long Luo ,  Tamara Schmitz ,  Jeremy Chritz ,  Jaime Cummins

    IPC: G06N3/08 ,  G06N3/04 ,  G06N3/045 ,  H04W4/02 ,  H04W4/38 ,  H04W4/40 ,  H04W4/90

    CPC classification number: G06N3/08 ,  G06N3/04 ,  G06N3/045 ,  H04W4/02 ,  H04W4/023 ,  H04W4/38 ,  H04W4/40 ,  H04W4/90

    Abstract: Systems, methods, and apparatuses related to cooperative learning neural networks are described. Cooperative learning neural networks may include neural networks which utilize sensor data received wirelessly from at least one other wireless communication device to train the neural network. For example, cooperative learning neural networks described herein may be used to develop weights which are associated with objects or conditions at one device and which may be transmitted to a second device, where they may be used to train the second device to react to such objects or conditions. The disclosed features may be used in various contexts, including machine-type communication, machine-to-machine communication, device-to-device communication, and the like. The disclosed techniques may be employed in a wireless (e.g., cellular) communication system, which may operate according to various standardized protocols.

    Methods and apparatus for performing diversity matrix operations within a memory array
    156.
    发明授权
    Methods and apparatus for performing diversity matrix operations within a memory array 有权

    公开(公告)号：US11853385B2

    公开(公告)日：2023-12-26

    申请号：US16705096

    申请日：2019-12-05

    Applicant: Micron Technology, Inc.

    Inventor： Fa-Long Luo

    IPC: G06F17/16 ,  G06F9/30 ,  G11C13/00 ,  G06F12/02

    CPC classification number: G06F17/16 ,  G06F9/3001 ,  G06F9/30036 ,  G06F12/0207 ,  G11C13/004 ,  G11C13/0069 ,  G06F2212/454

    Abstract: Methods and apparatus for performing diversity matrix operations within a memory fabric. Various embodiments of the present disclosure are directed to converting a memory array into a matrix fabric for spatial diversity-related matrix transformations and performing matrix operations therein. Exemplary embodiments described herein perform MIMO-related matrix transformations (e.g., precoding, beamforming, or data recovery matrix operations) within a memory device that includes a matrix fabric and matrix multiplication unit (MMU). In one variant, the matrix fabric uses a “crossbar” construction of resistive elements. Each resistive element stores a level of impedance that represents the corresponding matrix coefficient value. The crossbar connectivity can be driven with an electrical signal representing the input vector as an analog voltage. The resulting signals can be converted from analog voltages to a digital values by an MMU to yield a matrix-vector product. The MMU may additionally perform various other logical operations within the digital domain.

    Apparatuses and methods for ordering bits in a memory device
    157.
    发明授权
    Apparatuses and methods for ordering bits in a memory device 有权

    公开(公告)号：US11782721B2

    公开(公告)日：2023-10-10

    申请号：US17680538

    申请日：2022-02-25

    Applicant: Micron Technology, Inc.

    Inventor： Glen E. Hush ,  Aaron P. Boehm ,  Fa-Long Luo

    IPC: G06F9/38 ,  G06F9/30 ,  G11C7/10 ,  G11C7/08

    CPC classification number: G06F9/3855 ,  G06F9/3001 ,  G06F9/30018 ,  G11C7/08 ,  G11C7/1006 ,  G06F9/30032

    Abstract: Systems, apparatuses, and methods for organizing bits in a memory device are described. In a number of embodiments, an apparatus can include an array of memory cells, a data interface, a multiplexer coupled between the array of memory cells and the data interface, and a controller coupled to the array of memory cells, the controller configured to cause the apparatus to latch bits associated with a row of memory cells in the array in a number of sense amplifiers in a prefetch operation and send the bits from the sense amplifiers, through a multiplexer, to a data interface, which may include or be referred to as DQs. The bits may be sent to the DQs in a particular order that may correspond to a particular matrix configuration and may thus facilitate or reduce the complexity of arithmetic operations performed on the data.

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