公开(公告)号：US10725736B2

公开(公告)日：2020-07-28

申请号：US16115280

申请日：2018-08-28

Applicant: Micron Technology, Inc.

Inventor： Aaron P. Boehm

IPC: G06F12/16 ,  G06F7/20 ,  G06F1/30 ,  H03K19/173 ,  G06F3/06

Abstract: Apparatuses, systems, and methods related to determination of a match between data values stored by several arrays are described. A system using the data values may manage performance of functions, including automated functions critical for prevention of damage to a product, personnel safety, and/or reliable operation, based on whether the data values match. For instance, one apparatus described herein includes a plurality of arrays of memory cells formed on a single memory chip. The apparatus further includes comparator circuitry configured to compare data values stored by two arrays selected from the plurality to determine whether there is a match between the data values stored by the two arrays. The apparatus further includes an output component configured to output data values of one of the two arrays responsive to determination of the match between the data values stored by the two arrays.

公开(公告)号：US10666725B2

公开(公告)日：2020-05-26

申请号：US16142590

申请日：2018-09-26

Applicant: Micron Technology, Inc.

Inventor： Aaron P. Boehm

IPC: H01L29/08 ,  G06F15/173 ,  H04W4/46 ,  H04W84/18 ,  H04L29/08 ,  H04W92/18

Abstract: Apparatuses, systems, and methods related to a data center using a memory pool between selected memory resources are described. A data center using a memory pool between selected memory resources may enable performance of functions, including automated functions critical for prevention of damage to product, personal safety, and/or reliable operation, based on increased access to data that may improve performance of a mission profile. For instance, a method described herein includes transmitting, from a processor at a first vehicle that comprises the processor and memory, a request to access a pool of memory resources configured from a plurality of vehicles each having a local processor and memory, receiving, from a second vehicle of the plurality of vehicles, an indication to access the pool of memory resources, and reading data from or writing data to the memory at the second vehicle using the processor at the first vehicle based at least in part on receiving the indication to access the pool of memory resources.

公开(公告)号：US20200100079A1

公开(公告)日：2020-03-26

申请号：US16142172

申请日：2018-09-26

Applicant: Micron Technology, Inc.

Inventor： Aaron P. Boehm

IPC: H04W4/44 ,  H04L29/08

Abstract: Apparatuses, systems, and methods related to accessing a memory resource at one or more physically remote entities are described. A system accessing a memory resource at one or more physically remote entities may enable performance of functions, including automated functions critical for prevention of damage to a product, personnel safety, and/or reliable operation, based on increased access to data that may improve performance of a mission profile. For instance, one apparatus described herein includes a first vehicle configured to determine that a processing capability or a memory capacity, or both, at the first vehicle is insufficient to perform a processing operation at the first vehicle, identify additional processing resources or additional memory capacity, or both, at a second vehicle that is in wireless communication with the first vehicle based at least in part on determining that the processing capability or the memory capacity, or both, at the first vehicle is insufficient, and perform the processing operation at the first vehicle using the additional processing resources or the additional memory capacity, or both.

公开(公告)号：US20200081631A1

公开(公告)日：2020-03-12

申请号：US16546252

申请日：2019-08-20

Applicant: Micron Technology, Inc.

Inventor： Scott E. Schaefer ,  Aaron P. Boehm

IPC: G06F3/06

Abstract: Methods, systems, and devices for row hammer protection for a memory device are described. A memory device may identify a threshold of related row accesses (e.g., access commands or activates to a same row address or a row address space) for a memory array. In a first operation mode, the memory device may execute commands received from a host device on the memory array. The memory device may determine that a metric of the received row access commands satisfies the threshold of related row accesses. The memory device may switch the memory array from the first operation mode to a second operation mode based on satisfying the threshold. The second operation mode may restrict access to at least one row of the memory, while the first mode may be less restrictive. Additionally or alternatively, the memory device may notify the host device that the metric has satisfied the threshold.

公开(公告)号：US20190043545A1

公开(公告)日：2019-02-07

申请号：US15666375

申请日：2017-08-01

Applicant: Micron Technology, Inc.

Inventor： Aaron P. Boehm

IPC: G11C7/22

Abstract: A memory device is provided. The memory device includes one or more memories and a connector operably coupled to the one or more memories and configured to receive signals including a first reference clock signal from a connected host. The memory device further includes circuitry configured to determine a frequency of the first reference clock signal. The circuitry can be configured to generate a second reference clock signal and to compare the first and second reference clock signals to determine the frequency of the first reference clock signal. The memory devices can further include circuitry configured to adjust one or more operating characteristics of the memory device in response to the determined frequency of the first reference clock signal.

公开(公告)号：US20250158639A1

公开(公告)日：2025-05-15

申请号：US19020935

申请日：2025-01-14

Applicant: Micron Technology, Inc.

Inventor： Aaron P. Boehm ,  Scott E. Schaefer

IPC: H03M13/15 ,  H03M13/00 ,  H03M13/11

Abstract: Methods, systems, and devices for error detection and classification at a host device are described. A host device may communicate a read command for a codeword stored at a memory device. In response to communicating the read command, the host device may receive the codeword and an error indication bit that indicates whether the memory device detected an error in the codeword. The host device may use the codeword to generate a set of syndrome bits. The host device may determine an error status of the codeword based on the error indication bit for the codeword and the set of syndrome bits for the codeword.

公开(公告)号：US20240372566A1

公开(公告)日：2024-11-07

申请号：US18639692

申请日：2024-04-18

Applicant: Micron Technology, Inc.

Inventor： Scott E. Schaefer ,  Aaron P. Boehm

IPC: H03M13/15

Abstract: Methods, systems, and devices for selective modes for error control are described. A memory system may implement an error control engine supporting error correction operations and error detection operations. The error control engine may switch between an error correction mode and an error detection mode. The error control engine may receive data and error control information, generate additional error control information, and compare the received and generated error control information to detect one or more errors in the data. In some examples, the error control engine may be configured to operate in the error correction mode, and the error control engine may correct single-bit errors in the data. In other examples, the error control engine may be configured to operate in the error detection mode, and the error control engine may detect errors in the data and transmit an indication of the errors.

公开(公告)号：US20240250699A1

公开(公告)日：2024-07-25

申请号：US18594795

申请日：2024-03-04

Applicant: Micron Technology, Inc.

Inventor： Aaron P. Boehm ,  Scott E. Schaefer

IPC: H03M13/15 ,  G06F11/07 ,  H03M13/00

CPC classification number: H03M13/159 ,  G06F11/073 ,  G06F11/0787 ,  H03M13/611

Abstract: Methods, systems, and devices for managing error control information using a register are described. A memory device may store, at a register, an indication of whether the memory device has detected an error included in or otherwise associated with data requested from a host device. The memory device may determine to store the indication based on whether a communication protocol is enabled or disabled, and whether an error control configuration is enabled or disabled. The host device may request information from the register of the memory device, and the memory device may output the indication of whether the error was detected in response to the request.

公开(公告)号：US20240220361A1

公开(公告)日：2024-07-04

申请号：US18608460

申请日：2024-03-18

Applicant: Micron Technology, Inc.

Inventor： Scott E. Schaefer ,  Aaron P. Boehm

IPC: G06F11/10 ,  G06F11/07

CPC classification number: G06F11/1068 ,  G06F11/0772 ,  G06F11/0793

Abstract: Methods, systems, and devices for redundancy-based error detection in a memory device are described. A memory device may read multiple copies of a codeword from memory and generate for each codeword copy an error detection bit that indicates whether the memory device detected an error in that codeword. Additionally, the memory device may compare the codeword copies and generate one or more match bits that indicate whether corresponding portions of the codewords match. Using a combination of the error detection bits and the match bits, the memory device may determine the error status of each codeword.

公开(公告)号：US12014792B2

公开(公告)日：2024-06-18

申请号：US18108302

申请日：2023-02-10

Applicant: Micron Technology, Inc.

Inventor： Mark D. Ingram ,  Todd Jackson Plum ,  Scott E. Schaefer ,  Aaron P. Boehm ,  Scott D. Van De Graaff

IPC: G11C29/44 ,  G06F12/02 ,  G11C29/12

CPC classification number: G11C29/4401 ,  G06F12/0238 ,  G11C29/12005 ,  G11C29/12015 ,  G06F2212/7201 ,  G06F2212/7211 ,  G11C2207/2254

Abstract: Methods, systems, and devices for monitoring and adjusting access operations at a memory device are described to support integrating monitors or sensors for detecting memory device health issues, such as those resulting from device access or wear. The monitoring may include traffic monitoring of access operations performed at various components of the memory device, or may include sensors that may measure parameters of components of the memory device to detect wear. The traffic monitoring or the parameters measured by the sensors may be represented by a metric related to access operations for the memory device. The memory device may use the metric (e.g., along with a threshold) to determine whether to adjust a parameter associated with performing access operations received by the memory device, in order to implement a corrective action.