公开(公告)号：US11257553B2

公开(公告)日：2022-02-22

申请号：US17239397

申请日：2021-04-23

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Anh Ly ,  Thuan Vu

IPC: G11C16/00 ,  G11C16/34 ,  G11C16/04 ,  G11C16/10 ,  G11C16/08 ,  G11C16/16 ,  G11C16/28

Abstract: The present invention relates to a flash memory cell with only four terminals and a high voltage row decoder for operating an array of such flash memory cells. The invention allows for fewer terminals for each flash memory cell compared to the prior art, which results in a simplification of the decoder circuitry and overall die space required per flash memory cells. The invention also provides for the use of high voltages on one or more of the four terminals to allow for read, erase, and programming operations despite the lower number of terminals compared to prior art flash memory cells.

公开(公告)号：US20220004860A1

公开(公告)日：2022-01-06

申请号：US17140924

申请日：2021-01-04

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Thuan Vu ,  Stanley Hong ,  Stephen Trinh ,  Anh Ly ,  Nhan Do ,  Mark Reiten

IPC: G06N3/063 ,  G11C11/408 ,  G11C11/4074 ,  G11C11/406

Abstract: Numerous embodiments of analog neural memory arrays are disclosed. Certain embodiments comprise an adaptive bias decoder for providing additional bias to array input lines to compensate for instances where ground floats above 0V. This is useful, for example, to minimize the voltage drop for a read, program, or erase operation while maintaining accuracy in the operation.

公开(公告)号：US20210383869A1

公开(公告)日：2021-12-09

申请号：US17104385

申请日：2020-11-25

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Thuan Vu ,  Stanley Hong ,  Stephen Trinh ,  Anh Ly

IPC: G11C16/08 ,  G11C11/54 ,  G06N3/063

Abstract: Various embodiments of tandem row decoders are disclosed. Each embodiment of a tandem row decoder comprises a word line decoder and a control gate decoder. The tandem row decoder exhibits reduced leakage current on the word line and the control gate line when the tandem row decoder is not enabled.

公开(公告)号：US20210350217A1

公开(公告)日：2021-11-11

申请号：US17090481

申请日：2020-11-05

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Thuan Vu ,  Stanley Hong ,  Stephen Trinh ,  Vipin Tiwari ,  Han Tran ,  Hien Pham

IPC: G06N3/063

Abstract: Numerous embodiments of analog neural memory arrays are disclosed. Certain embodiments contain improved mechanisms for pulling source lines down to ground expeditiously. This is useful, for example, to minimize the voltage drop for a read, program, or erase operation.

公开(公告)号：US20210305264A1

公开(公告)日：2021-09-30

申请号：US17069563

申请日：2020-10-13

Applicant: Silicon Storage Technology, Inc.

Inventor： Feng Zhou ,  Xian Liu ,  Steven Lemke ,  Hieu Van Tran ,  Nhan Do

IPC: H01L27/11529 ,  H01L27/11551 ,  H01L29/66 ,  H01L29/423

Abstract: Memory cells formed on upwardly extending fins of a semiconductor substrate, each including source and drain regions with a channel region therebetween, a floating gate extending along the channel region and wrapping around the fin, a word line gate extending along the channel region and wrapping around the fin, a control gate over the floating gate, and an erase gate over the source region. The control gates are a continuous conductive strip of material. First and second fins are spaced apart by a first distance. Third and fourth fins are spaced apart by a second distance. The second and third fins are spaced apart by a third distance greater than the first and second distances. The continuous strip includes a portion disposed between the second and third fins, but no portion of the continuous strip is disposed between the first and second fins nor between the third and fourth fins.

公开(公告)号：US20210287065A1

公开(公告)日：2021-09-16

申请号：US17238077

申请日：2021-04-22

Applicant: Silicon Storage Technology, Inc. ,  The Regents of the University of California

Inventor： Farnood Merrikh Bayat ,  Xinjie Guo ,  Dmitri Strukov ,  Nhan Do ,  Hieu Van Tran ,  Vipin Tiwari ,  Mark Reiten

IPC: G06N3/04 ,  G06N3/063 ,  G06F3/06

Abstract: A number of circuits for use in an output block coupled to a non-volatile memory array in a neural network are disclosed. The embodiments include a circuit for converting an output current from a neuron in a neural network into an output voltage, a circuit for converting a voltage received on an input node into an output current, a circuit for summing current received from a plurality of neurons in a neural network, and a circuit for summing current received from a plurality of neurons in a neural network.

公开(公告)号：US20210257026A1

公开(公告)日：2021-08-19

申请号：US17191392

申请日：2021-03-03

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Thuan Vu ,  Stanley Hong ,  Anh Ly ,  Vipin Tiwari ,  Nhan Do

IPC: G11C16/04 ,  G06N3/08 ,  H01L27/11521 ,  H01L29/788

Abstract: Numerous embodiments are disclosed for a high voltage generation algorithm and system for generating high voltages necessary for a particular programming operation in analog neural memory used in a deep learning artificial neural network. Compensation measures can be utilized that compensate for changes in voltage or current as the number of cells being programmed changes.

公开(公告)号：US20210209458A1

公开(公告)日：2021-07-08

申请号：US17185725

申请日：2021-02-25

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  STEVEN LEMKE ,  NHAN DO ,  MARK REITEN

IPC: G06N3/063 ,  G06F17/16

Abstract: Numerous embodiments of a precision programming algorithm and apparatus are disclosed for precisely and quickly depositing the correct amount of charge on the floating gate of a non-volatile memory cell within a vector-by-matrix multiplication (VMM) array in an artificial neural network. Selected cells thereby can be programmed with extreme precision to hold one of N different values.

公开(公告)号：US20210209456A1

公开(公告)日：2021-07-08

申请号：US16829757

申请日：2020-03-25

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Steven Lemke ,  Vipin Tiwari ,  Nhan Do ,  Mark Reiten

IPC: G06N3/063 ,  G11C11/54 ,  G11C11/56 ,  G06F17/16 ,  G06F1/03

Abstract: Numerous embodiments of a precision programming algorithm and apparatus are disclosed for precisely and quickly depositing the correct amount of charge on the floating gate of a non-volatile memory cell within a vector-by-matrix multiplication (VMM) array in an artificial neural network. Selected cells thereby can be programmed with extreme precision to hold one of N different values.

公开(公告)号：US11031050B2

公开(公告)日：2021-06-08

申请号：US16526987

申请日：2019-07-30

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran

IPC: G11C7/06 ,  G11C7/02 ,  G11C16/28 ,  G11C11/56 ,  G11C16/04 ,  G11C5/14 ,  G11C11/4091 ,  G11C16/30

Abstract: In one aspect, the invention concerns a memory system that compensates for power level variations in sense amplifiers for multilevel memory. For example, a compensation circuit can be employed to compensate for current or voltage variations in the power supplied to multilevel memory sense amplifiers. As another example, compensation can be accomplished by application of a bias voltage to the power supply. Another example is a sense amplifier configured with improved input common mode voltage range. Such sense amplifiers can be two-pair and three-pair sense amplifiers. Further examples of the invention include more simplified sense amplifier configurations, and sense amplifiers having reduced leakage current.