公开(公告)号：US20140082443A1

公开(公告)日：2014-03-20

申请号：US14085300

申请日：2013-11-20

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Lee D. Whetsel

IPC: G01R31/3177

CPC classification number: G01R31/3177 ,  G01R31/318505 ,  G01R31/318544

Abstract: Scan testing of plural target electrical circuits, such as circuits 1 through N, becomes accelerated by using the scan test response data output from one circuit, such as circuit 1, as the scan test stimulus data for another circuit, such as circuit 2. After reset, a scan path captures the output response data from the reset stimulus from all circuits. A tester then shifts the captured data only the length of the first circuit's scan path while loading the first circuit's scan path with new test stimulus data. The new response data from all the circuits then is captured in the scan path. This shift and capture cycle is repeated until the first circuit is tested. The first circuit is then disabled and any remaining stimulus data is applied to the second circuit. This process is repeated until all the circuits are tested. A data retaining boundary scan cell used in the scan testing connects the output of an additional multiplexer as the input to a boundary cell. The inputs of the additional multiplexer connect to the data input and data output of the boundary cell.

Abstract translation: 通过使用从诸如电路1的一个电路输出的扫描测试响应数据作为诸如电路2的另一电路的扫描测试激励数据，来加速诸如电路1至N的多个目标电路的扫描测试。 复位时，扫描路径从所有电路的复位激励中捕获输出响应数据。 然后，测试者将捕获的数据仅移动第一电路的扫描路径的长度，同时用新的测试激励数据加载第一电路的扫描路径。 然后在扫描路径中捕获来自所有电路的新的响应数据。 重复该移位和捕获周期直到第一个电路被测试。 然后禁用第一电路，并且将任何剩余的激励数据施加到第二电路。 重复该过程直到所有电路都被测试。 在扫描测试中使用的数据保留边界扫描单元将附加多路复用器的输出连接到边界单元的输入。 附加多路复用器的输入连接到边界单元的数据输入和数据输出。

公开(公告)号：US20140068363A1

公开(公告)日：2014-03-06

申请号：US14074402

申请日：2013-11-07

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Lee D. Whetsel

IPC: G01R31/3185

CPC classification number: G01R31/3177 ,  G01R31/31703 ,  G01R31/318511 ,  G01R31/318533 ,  G01R31/318536 ,  G01R31/318541 ,  G01R31/318544 ,  G01R31/318566 ,  G01R31/318572 ,  G01R31/31926 ,  G01R31/31932 ,  G06F11/26 ,  G06F11/277

Abstract: A test controller applies test stimulus signals to the input pads of plural die on a wafer in parallel. The test controller also applies encoded test response signals to the output pads of the plural die in parallel. The encoded test response signals are decoded on the die and compared to core test response signals produced from applying the test stimulus signals to core circuits on the die. The comparison produces pass/fail signals that are loaded in to scan cells of an IEEE 1149.1 scan path. The pass/fail signals then may be scanned out of the die to determine the results of the test.

Abstract translation: 测试控制器将测试激励信号并行地施加到晶片上的多个管芯的输入焊盘。 测试控制器还将编码的测试响应信号并行地应用于多个管芯的输出焊盘。 编码的测试响应信号在芯片上解码，并与通过将测试激励信号应用于芯片上的核心电路产生的核心测试响应信号进行比较。 该比较产生加载到IEEE 1149.1扫描路径的扫描单元中的通过/失败信号。 然后可以将通过/失败信号扫描出模具以确定测试结果。

公开(公告)号：US08667351B2

公开(公告)日：2014-03-04

申请号：US13892473

申请日：2013-05-13

Applicant: Texas Instruments Incorporated

Inventor： Lee D. Whetsel

IPC: G01R31/28

CPC classification number: G01R31/3177 ,  G01R31/31713 ,  G01R31/31723 ,  G01R31/31727 ,  G01R31/318508 ,  G01R31/318555

Abstract: A test architecture accesses IP core test wrappers within an IC using a Link Instruction Register (LIR). An IEEE P1500 standard is in development for providing test access to these individual cores via a test structure called a wrapper. The wrapper resides at the boundary of the core and provides a way to test the core and the interconnections between cores. The test architecture enables each of the plural wrappers in the IC, including wrappers in cores embedded within other cores, with separate enable signals.

Abstract translation: 测试架构使用链接指令寄存器（LIR）访问IC内的IP核测试包装器。 正在开发IEEE P1500标准，通过称为包装器的测试结构提供对这些单独内核的测试访问。 包装器位于核心的边界处，并提供了一种测试核心和核心之间互连的方法。 测试架构使得IC中的多个包装器中的每一个包括嵌入在其他核心内的核心中的包装器，具有单独的使能信号。

公开(公告)号：US08635504B2

公开(公告)日：2014-01-21

申请号：US13757361

申请日：2013-02-01

Applicant: Texas Instruments Incorporated

Inventor： Lee D. Whetsel

IPC: G01R31/28

CPC classification number: G01R31/31723 ,  G01R31/317 ,  G01R31/31705 ,  G01R31/31727 ,  G01R31/3177 ,  G01R31/318533 ,  G01R31/318536 ,  G01R31/318591 ,  G01R31/318597 ,  G06F11/267

Abstract: The present disclosure describes using the JTAG Tap's TMS and/or TCK terminals as general purpose serial Input/Output (I/O) Manchester coded communication terminals. The Tap's TMS and/or TCK terminal can be used as a serial I/O communication channel between; (1) an IC and an external controller, (2) between a first and second IC, or (3) between a first and second core circuit within an IC. The use of the TMS and/or TCK terminal as serial I/O channels, as described, does not effect the standardized operation of the JTAG Tap, since the TMS and/or TCK I/O operations occur while the Tap is placed in a non-active steady state.

Abstract translation: 本公开描述了使用JTAG Tap的TMS和/或TCK终端作为通用串行输入/输出（I / O）曼彻斯特编码通信终端。 Tap的TMS和/或TCK终端可以用作串行I / O通信通道; （1）IC和外部控制器，（2）在第一和第二IC之间，或（3）IC内的第一和第二核心电路之间。 如上所述，使用TMS和/或TCK端子作为串行I / O通道不会影响JTAG Tap的标准化操作，因为TMS和/或TCK I / O操作发生在Tap被放置在 非活跃稳态。

公开(公告)号：US08634508B2

公开(公告)日：2014-01-21

申请号：US13664022

申请日：2012-10-30

Applicant: Texas Instruments Incorporated

Inventor： Lee D. Whetsel

IPC: H04L7/00

CPC classification number: G06F13/4291 ,  G01R31/31725 ,  G01R31/31726 ,  G01R31/318536 ,  G01R31/318594 ,  G06F1/04 ,  G06F1/06 ,  H04B1/18 ,  H04J3/0644 ,  H04L7/0008

Abstract: Data is communicated through two separate circuits or circuit groups, each having clock and mode inputs, by sequentially reversing the role of the clock and mode inputs. The data communication circuits have data inputs, data outputs, a clock input for timing or synchronizing the data input and/or output communication, and a mode input for controlling the data input and/or output communication. A clock/mode signal connects to the clock input of one circuit and to the mode input of the other circuit. A mode/clock signal connects to the mode input of the one circuit and to the clock input of the other circuit. The role of the mode and clock signals on the mode/clock and clock/mode signals, or their reversal, selects one or the other of the data communication circuits.

Abstract translation: 数据通过两个单独的电路或电路组进行通信，每个电路或电路组通过顺序地反转时钟和模式输入的作用而具有时钟和模式输入。 数据通信电路具有数据输入，数据输出，用于定时或同步数据输入和/或输出通信的时钟输入，以及用于控制数据输入和/或输出通信的模式输入。 时钟/模式信号连接到一个电路的时钟输入和另一个电路的模式输入。 模式/时钟信号连接到一个电路的模式输入和另一个电路的时钟输入。 模式和时钟信号对模式/时钟和时钟/模式信号或其反相的作用选择数据通信电路中的一个或另一个。

公开(公告)号：US08627161B2

公开(公告)日：2014-01-07

申请号：US13757305

申请日：2013-02-01

Applicant: Texas Instruments Incorporated

Inventor： Lee D. Whetsel

IPC: G01R31/28

CPC classification number: G01R31/318536 ,  G01R31/31721 ,  G01R31/31723 ,  G01R31/3177 ,  G01R31/318575 ,  G01R31/318577

Abstract: Scan architectures are commonly used to test digital circuitry in integrated circuits. The present disclosure describes a method of adapting conventional scan architectures into a low power scan architecture. The low power scan architecture maintains the test time of conventional scan architectures, while requiring significantly less operational power than conventional scan architectures. The low power scan architecture is advantageous to IC/die manufacturers since it allows a larger number of circuits (such as DSP or CPU core circuits) embedded in an IC/die to be tested in parallel without consuming too much power within the IC/die. Since the low power scan architecture reduces test power consumption, it is possible to simultaneously test more die on a wafer than previously possible using conventional scan architectures. This allows wafer test times to be reduced which reduces the manufacturing cost of each die on the wafer.

Abstract translation: 扫描架构通常用于测试集成电路中的数字电路。 本公开描述了将常规扫描架构适应成低功耗扫描架构的方法。 低功耗扫描架构保持常规扫描架构的测试时间，同时要求比传统扫描架构明显更低的运行能力。 低功耗扫描架构对于IC /模具制造商是有利的，因为它允许并行测试嵌入在IC /管芯中的更多数量的电路（例如DSP或CPU核心电路），而不消耗IC /管芯内的太多功率 。 由于低功耗扫描架构降低了测试功耗，因此可以使用传统的扫描架构在以前可能的同时测试晶片上的更多裸片。 这允许减少晶片测试时间，这降低了晶片上每个芯片的制造成本。

公开(公告)号：US08621297B2

公开(公告)日：2013-12-31

申请号：US13891885

申请日：2013-05-10

Applicant: Texas Instruments Incorporated

Inventor： Lee D. Whetsel

IPC: G01R31/28

CPC classification number: G01R31/3177 ,  G01R31/31715 ,  G01R31/318505 ,  G01R31/318511 ,  G01R31/318533 ,  G01R31/318558 ,  G01R31/318572 ,  G01R31/318594 ,  G11C29/006 ,  G11C29/022 ,  G11C29/48 ,  G11C2029/3202

Abstract: The peripheral circuitry (350, 360, ESD, BH) of an integrated circuit die on a wafer is tested without physically contacting the bond pads of the die.

Abstract translation: 测试晶片上的集成电路管芯的外围电路（350,360，ESD，BH），而不会物理接触管芯的接合焊盘。

公开(公告)号：US20130311842A1

公开(公告)日：2013-11-21

申请号：US13948801

申请日：2013-07-23

Applicant: Texas Instruments Incorporated

Inventor： Lee D. Whetsel

IPC: G01R31/3177

CPC classification number: G01R31/3177 ,  G01R31/31715 ,  G01R31/3172 ,  G01R31/31725 ,  G01R31/318547

Abstract: The disclosure describes novel methods and apparatuses for controlling a device's TCA circuit when the device exists in a JTAG daisy-chain arrangement with other devices. The methods and apparatuses allow the TCA test pattern set used during device manufacturing to be reused when the device is placed in a JTAG daisy-chain arrangement with other devices, such as in a customers system using the device. Additional embodiments are also provided and described in the disclosure.

公开(公告)号：US08589748B2

公开(公告)日：2013-11-19

申请号：US13693593

申请日：2012-12-04

Applicant: Texas Instruments Incorporated

Inventor： Lee D. Whetsel

IPC: G01R31/28

CPC classification number: G01R31/3177 ,  G01R31/28 ,  G01R31/318555 ,  G01R31/318572

Abstract: Today many instances of IEEE 1149.1 Tap domains are included in integrated circuits (ICs). While all TAP domains may be serially connected on a scan path that is accessible external to the IC, it is generally preferred to have selectivity on which Tap domain or Tap domains are accessed. Therefore Tap domain selection circuitry may be included in ICs and placed in the scan path along with the Tap domains. Ideally, the Tap domain selection circuitry should only be present in the scan path when it is necessary to modify which Tap domains are selected in the scan path. The present disclosure describes a novel method and apparatus which allows the Tap domain selection circuitry to be removed from the scan path after it has been used to select Tap domains and to be replaced back into the scan path when it is necessary to select different Tap domains.

Abstract translation: 今天，许多IEEE 1149.1 Tap域的实例都包含在集成电路（IC）中。 虽然所有TAP域可以在可在IC外部访问的扫描路径上串行连接，但通常优选具有访问Tap域或Tap域的选择性。 因此，点选区域选择电路可能包含在IC中，并与Tap域一起放置在扫描路径中。 理想情况下，如果需要修改在扫描路径中选择了哪个Tap域，则Tap域选择电路应该仅存在于扫描路径中。 本公开描述了一种新颖的方法和装置，其允许在其已经用于选择分组域之后从扫描路径移除分接区域选择电路，并且当需要选择不同的分接区域时，将其替换回扫描路径 。

公开(公告)号：US20130305109A1

公开(公告)日：2013-11-14

申请号：US13941717

申请日：2013-07-15

Applicant: Texas Instruments Incorporated

Inventor： Lee D. Whetsel

IPC: G01R31/3177

CPC classification number: G01R31/3177 ,  G01R31/318555 ,  G01R31/318558 ,  G01R31/318561 ,  G01R31/318563 ,  G01R31/318572

Abstract: An integrated circuit can have plural core circuits, each having a test access port that is defined in IEEE standard 1149.1. Access to and control of these ports is though a test linking module. The test access ports on an integrated circuit can be arranged in a hierarchy with one test linking module controlling access to plural secondary test linking modules and test access ports. Each secondary test linking module in turn can also control access to tertiary test linking modules and test access ports. The test linking modules can also be used for emulation.