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公开(公告)号：US11842009B2
公开(公告)日：2023-12-12
申请号：US17677119
申请日：2022-02-22
Inventor： Bowei Chen , Yue Ding , Guodong Sun
IPC: G06F3/041 , G06F3/044 , H03M1/20 , H04L65/00 , H04N21/462
CPC classification number: G06F3/0418 , G06F3/0412 , G06F3/0446 , G06F3/0447 , H03M1/20 , H04L65/00 , H04N21/4621
Abstract: A method for operating an electronic device includes detecting, by a touchscreen controller, a touch point on a touchscreen; determining, by the touchscreen controller, coordinates of the touch point; scaling, by the touchscreen controller, up the coordinates of the touch point to obtain scaled up coordinates by overwriting a reserved portion of a touch event protocol with additional information corresponding to the coordinates of the touch point; reporting, by the touchscreen controller, the scaled up coordinates of the touch point to an application processor; and determining, by the application processor, the coordinates of the touch point with an increased resolution by converting the scaled up coordinates into a floating point value.
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公开(公告)号：US20230378923A1
公开(公告)日：2023-11-23
申请号：US17747845
申请日：2022-05-18
Inventor： Jian Wen , Davide Luigi Brambilla , Qiyu Liu , Mei Yang , Shuming Tong , Francesco Stilgenbauer
CPC classification number: H03G3/3026 , H03G3/348 , H03G3/3036 , H03K4/06
Abstract: In an embodiment, an amplifier circuit includes a second stage that includes a first switch circuit including first and second terminals, a plurality of resistive elements coupled between the first and second terminals of the first switch circuit, and a plurality of switches configured to control an equivalent resistance between the first and second terminals of the first switch circuit. During play mode, the second stage has a gain between the input of the second stage and the output of the second stage of a first value. During a transition from mute mode to play mode, the amplifier circuit is configured to progressively increase the gain of the second stage from a second value to the first value. During a transition from play mode to mute mode, the amplifier circuit is configured to progressively decrease the gain of the second stage from the first value to the second value.
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公开(公告)号：US11757345B2
公开(公告)日：2023-09-12
申请号：US17646934
申请日：2022-01-04
Applicant: STMicroelectronics (Shenzhen) R&D Co. Ltd.
Inventor： Dino Costanzo , Xiyu Xu , Chengpan Cai
CPC classification number: H02M1/0009 , H02M7/493 , H02P5/505 , H02P5/685
Abstract: An apparatus includes a first inverter configured to drive a first motor having a plurality of phases, the first inverter comprising a plurality of inverter legs, each of which is coupled to a corresponding phase of the first motor, a second inverter configured to drive a second motor having a plurality of phases, the second inverter comprising a plurality of inverter legs, each of which is coupled to a corresponding phase of the second motor, and a first current sensor configured to sense currents flowing in the first inverter and the second inverter, wherein the first current sensor is shared by at least by two inverter legs.
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公开(公告)号：US11750163B2
公开(公告)日：2023-09-05
申请号：US17200490
申请日：2021-03-12
Applicant: STMicroelectronics (Shenzhen) R&D Co. Ltd.
Inventor： Ru Feng Du , Qi Yu Liu
IPC: H03F3/217 , H03G1/04 , H03K19/017 , H03K19/20 , H03K19/003 , H03G3/30 , H03K19/096
CPC classification number: H03G1/04 , H03F3/2173 , H03G3/3026 , H03K19/00323 , H03K19/01728 , H03K19/096 , H03K19/20 , H03F2200/78
Abstract: In an embodiment, a class-D amplifier includes an input terminal configured to receive an input signal; a comparator having an input coupled to the input terminal; a deglitching circuit having an input coupled to an output of the comparator; and a driving circuit having an input coupled to an output of the deglitching circuit. The deglitching circuit includes a logic circuit coupled between the input of the deglitching circuit and the output of the deglitching circuit. The logic circuit is configured to receive a clock signal having the same frequency as the switching frequency of the class-D amplifier.
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公开(公告)号：US20230019962A1
公开(公告)日：2023-01-19
申请号：US17374815
申请日：2021-07-13
Inventor： Mirko Guarnera , Wenbin Yang , Enrico Rosario Alessi , Fabio Passaniti
Abstract: A system and method for determining handedness in a device. The system including a first electrode, a second electrode, a sensor, and a processing circuit coupled to each other. The first electrode is placed at a first location, and the second electrode is placed at a second location on the device—the first location is different from the second location. The electrodes are configured to sense a variation in an electrostatic field in response to a user interacting with the device. The sensor detects a differential potential between the first electrode and the second electrode, and the processing circuit determines whether the user is interacting with the device using a left hand or a right hand. The determining is based on data received from the sensor corresponding to the differential potential.
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Patent Agency Ranking
公开(公告)号：US11496185B2
公开(公告)日：2022-11-08
申请号：US17024270
申请日：2020-09-17
Inventor： Wenhe Zhao , Jiasheng Wang
Abstract: A method for modulating a signal including operating a circuit in a first arrangement during a first operating interval and switching the circuit between the first arrangement and a second arrangement during a first modulation interval to vary a load on the circuit to produce a first amplitude shift keying (ASK) signal. The method further includes detecting a voltage on the circuit crossing a threshold level and operating the circuit in the second arrangement during a second operating interval. The method also includes switching the circuit between the second arrangement and the first arrangement during a second modulation interval to vary the load on the circuit to produce a second ASK signal.
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公开(公告)号：US11486928B2
公开(公告)日：2022-11-01
申请号：US17159511
申请日：2021-01-27
Inventor： Ignazio Pisello , Yu Yong Wang , Dario Arena , Qi Yu Liu
IPC: G01R31/3185 , G01R31/317 , G06F1/06
Abstract: A combinational circuit block has input pins configured to receive input digital signals and output pins configured to provide output digital signals as a function of the input digital signals received. A test input pin receives a test input signal. A test output pin provides a test output signal as a function of the test input signal received. A set of scan registers are selectively coupled to either the combinational circuit block or to one another so as to form a scan chain of scan registers serially coupled between the test input pin and the test output pin. The scan registers in the set of scan registers are clocked by a clock signal. At least one input register is coupled between the test input pin and a first scan register of the scan chain. The at least one input register is clocked by an inverted replica of the clock signal.
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公开(公告)号：US11303271B2
公开(公告)日：2022-04-12
申请号：US16991126
申请日：2020-08-12
Applicant: STMicroelectronics (Shenzhen) R&D Co. Ltd.
Inventor： Hong Wu Lin
Abstract: A filtering circuit for filtering a pulse width modulated (PWM) signal includes a D flip-flop having an input terminal configured to be coupled to a logic high signal and having an output terminal coupled to an output terminal of the filtering circuit; and a circuit coupled between an input terminal of the filtering circuit and the D flip-flop, the circuit configured to, for a first pulse of the PWM signal having a duty cycle within a pre-determined range: generate a positive pulse at a clock terminal of the D flip-flop as a clock signal of the D flip-flop; and generate a negative pulse at a reset terminal of the D flip-flop as a reset signal of the D flip-flop, wherein a duration between a rising edge of the positive pulse and a falling edge of the negative pulse is equal to a duration of the first pulse of the PWM signal.
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公开(公告)号：US20220085848A1
公开(公告)日：2022-03-17
申请号：US17024270
申请日：2020-09-17
Inventor： Wenhe Zhao , Jiasheng Wang
Abstract: A method for modulating a signal including operating a circuit in a first arrangement during a first operating interval and switching the circuit between the first arrangement and a second arrangement during a first modulation interval to vary a load on the circuit to produce a first amplitude shift keying (ASK) signal. The method further includes detecting a voltage on the circuit crossing a threshold level and operating the circuit in the second arrangement during a second operating interval. The method also includes switching the circuit between the second arrangement and the first arrangement during a second modulation interval to vary the load on the circuit to produce a second ASK signal.
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公开(公告)号：US11095170B1
公开(公告)日：2021-08-17
申请号：US16931111
申请日：2020-07-16
Applicant: STMicroelectronics (Shenzhen) R&D Co. Ltd.
Inventor： Jiasheng Wang
Abstract: A system and method for improving ASK packet transfer reliability and power dissipation efficiency at light-load or no-load conditions of a receiving device is provided. In an embodiment, the receiving device includes a dissipating element coupled to a rectifier. The dissipating element is connected to a reference voltage at a first duration corresponding to a transmission of the ASK packet. The dissipating element is disconnected from the reference voltage a second duration corresponding to an end of the transmission of the ASK packet.
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