公开(公告)号：US09270855B2

公开(公告)日：2016-02-23

申请号：US13430661

申请日：2012-03-26

Applicant: Mirko Guarnera ,  Alfio Castorina ,  Giuseppe Spampinato ,  Osvaldo M. Colavin ,  John Bloomfield ,  Armand Hekimian ,  Beátrice Varichon

Inventor： Mirko Guarnera ,  Alfio Castorina ,  Giuseppe Spampinato ,  Osvaldo M. Colavin ,  John Bloomfield ,  Armand Hekimian

IPC: G06F3/12 ,  H04N1/04 ,  H04N1/207 ,  H04N1/195

CPC classification number: H04N1/0461 ,  H04N1/195 ,  H04N1/207 ,  H04N2201/0414 ,  H04N2201/0416

Abstract: An embodiment of an integrated scanner apparatus, includes a support surface for objects to be scanned, a scanner unit to perform a scanning movement relative to the support surface to capture images of portions of objects to be scanned, and a printer unit carried by a carriage mobile with respect to said support surface, wherein said scanner unit is carried by said carriage carrying said printer unit to be imparted said scanning movement by said carriage.

Abstract translation: 集成扫描仪装置的实施例包括用于待扫描的对象的支撑表面，扫描器单元，用于执行相对于支撑表面的扫描运动，以捕获待扫描物体的部分的图像;以及打印机单元，其由托架 可移动地支撑所述支撑表面，其中所述扫描器单元由携带所述打印机单元的托架承载，以由所述托架赋予所述扫描运动。

公开(公告)号：US09263338B2

公开(公告)日：2016-02-16

申请号：US14060874

申请日：2013-10-23

Applicant: STMicroelectronics, Inc. ,  GLOBALFOUNDRIES INC.

Inventor： Qing Liu ,  Xiuyu Cai ,  Ruilong Xie

IPC: H01L21/00 ,  H01L21/8234 ,  H01L27/088

CPC classification number: H01L21/823412 ,  H01L21/823431 ,  H01L21/823481 ,  H01L21/823487 ,  H01L27/0886

Abstract: A method for making a semiconductor device may include forming, on a substrate, at least one stack of alternating first and second semiconductor layers. The first semiconductor layer may comprise a first semiconductor material and the second semiconductor layer may comprise a second semiconductor material. The first semiconductor material may be selectively etchable with respect to the second semiconductor material. The method may further include removing portions of the at least one stack and substrate to define exposed sidewalls thereof, forming respective spacers on the exposed sidewalls, etching recesses through the at least one stack and substrate to define a plurality of spaced apart pillars, selectively etching the first semiconductor material from the plurality of pillars leaving second semiconductor material structures supported at opposing ends by respective spacers, and forming at least one gate adjacent the second semiconductor material structures.

Abstract translation: 制造半导体器件的方法可以包括在衬底上形成交替的第一和第二半导体层的至少一个叠层。 第一半导体层可以包括第一半导体材料，第二半导体层可以包括第二半导体材料。 第一半导体材料可以相对于第二半导体材料可选择性地蚀刻。 该方法还可以包括去除至少一个堆叠和衬底的部分以限定其暴露的侧壁，在暴露的侧壁上形成相应的间隔物，蚀刻通过至少一个堆叠和衬底的凹槽以限定多个间隔开的柱，选择性蚀刻 来自多个柱的第一半导体材料离开第二半导体材料结构，在相对端通过相应的间隔件支撑，并且形成与第二半导体材料结构相邻的至少一个栅极。

公开(公告)号：US09245953B2

公开(公告)日：2016-01-26

申请号：US14597457

申请日：2015-01-15

Applicant: STMICROELECTRONICS, INC.

Inventor： Nicolas Loubet ,  Pierre Morin

IPC: H01L21/8238 ,  H01L29/15 ,  H01L29/78 ,  H01L29/66 ,  H01L29/10 ,  H01L29/16 ,  H01L29/165

CPC classification number: H01L29/7848 ,  H01L29/1054 ,  H01L29/155 ,  H01L29/16 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

Abstract: Methods and structures for forming strained-channel finFETs are described. Fin structures for finFETs may be formed in two epitaxial layers that are grown over a bulk substrate. A first thin epitaxial layer may be cut and used to impart strain to an adjacent channel region of the finFET via elastic relaxation. The structures exhibit a preferred design range for increasing induced strain and uniformity of the strain over the fin height.

公开(公告)号：US09240908B2

公开(公告)日：2016-01-19

申请号：US13284890

申请日：2011-10-29

Applicant: Muralidhar Karthik ,  George A. Vlantis

Inventor： Muralidhar Karthik ,  George A. Vlantis

IPC: H04L27/00 ,  H04L25/02 ,  H04L25/03 ,  H04L27/26

CPC classification number: H04L25/022 ,  H04L25/0204 ,  H04L25/0224 ,  H04L25/03821 ,  H04L27/2601

Abstract: In an embodiment, a transmitter includes first and second transmission paths. The first transmission path is configurable to generate first pilot clusters each including a respective first pilot subsymbol in a first cluster position, and the second transmission path is configurable to generate second pilot clusters each including a respective second pilot subsymbol in a second cluster position such that a vector formed by the first pilot subsymbols is orthogonal to a vector formed by the second pilot subsymbols. For example, where such a transmitter transmits simultaneous orthogonal-frequency-division-multiplexed (OFDM) signals (e.g., MIMO-OFDM signals) over respective channels that may impart inter-carrier interference (ICI) to the signals due to Doppler spread, the pattern of the pilot symbols that compose the pilot clusters may allow a receiver of these signals to use a recursive algorithm, such as a Vector State Scalar Observation (VSSO) Kalman algorithm, to estimate the responses of these channels.

Abstract translation: 在一个实施例中，发射机包括第一和第二传输路径。 第一传输路径可配置为产生第一导频簇，每个导频簇包括在第一簇位置中的相应的第一导频子符号，并且第二传输路径可配置为生成第二导频簇，每个导频簇包括第二簇位置中的相应的第二导频子符号，使得 由第一导频子符号形成的向量与由第二导频子符号形成的向量正交。 例如，在这种发射机通过可能由于多普勒扩展而给予信号的载波间干扰（ICI）的相应信道上发射同时正交频分复用（OFDM）信号（例如，MIMO-OFDM信号）的情况下， 构成导频簇的导频符号的模式可以允许这些信号的接收机使用诸如矢量状态标量观测（VSSO）卡尔曼算法的递归算法来估计这些信道的响应。

公开(公告)号：US09240454B1

公开(公告)日：2016-01-19

申请号：US14520781

申请日：2014-10-22

Applicant: STMicroelectronics, Inc.

Inventor： Qing Liu ,  Walter Kleemeier

IPC: H01L27/12 ,  H01L29/00 ,  H01L21/82 ,  H01L29/45 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/78 ,  H01L29/778

CPC classification number: H01L21/823814 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02584 ,  H01L21/8238 ,  H01L21/823821 ,  H01L21/823871 ,  H01L21/84 ,  H01L27/092 ,  H01L27/0924 ,  H01L27/1203 ,  H01L27/1211 ,  H01L29/45 ,  H01L29/456 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/778 ,  H01L29/7789 ,  H01L29/7838

Abstract: An integrated circuit includes a substrate supporting a transistor having a source region and a drain region. A high dopant concentration delta-doped layer is present on the source region and drain region of the transistor. A set of contacts extend through a pre-metal dielectric layer covering the transistor. A silicide region is provided at a bottom of the set of contacts. The silicide region is formed by a salicidation reaction between a metal present at the bottom of the contact and the high dopant concentration delta-doped layer on the source region and drain region of the transistor.

Abstract translation: 集成电路包括支撑具有源极区和漏极区的晶体管的衬底。 晶体管的源极区和漏极区存在高掺杂浓度的δ掺杂层。 一组触点延伸穿过覆盖晶体管的预金属介电层。 硅化物区域设置在该组触点的底部。 硅化物区域由接触底部存在的金属与晶体管的源极区域和漏极区域上的高掺杂浓度δ-掺杂层之间的水化反应形成。

公开(公告)号：US20160013206A1

公开(公告)日：2016-01-14

申请号：US14771016

申请日：2013-02-28

Applicant: COMMISSARIAT Á L'ÉNERGIE ATOMIQUE ET AUX ÉNERGIES ALTERNATIVES ,  INTERNATIONAL BUSINESS MACHINES CORPORATION ,  STMICROELECTRONICS, INC.

Inventor： Maud VINET ,  Kangguo CHENG ,  Bruce DORIS ,  Laurent GRENOUILLET ,  Ali KHAKIFIROOZ ,  Yannick LE TIEC ,  Qing LIU

IPC: H01L27/12 ,  H01L21/265 ,  H01L27/092 ,  H01L21/84 ,  H01L21/762 ,  H01L29/06 ,  H01L21/223

CPC classification number: H01L27/1203 ,  H01L21/2236 ,  H01L21/26513 ,  H01L21/76229 ,  H01L21/76237 ,  H01L21/823878 ,  H01L21/823892 ,  H01L21/84 ,  H01L27/0928 ,  H01L29/0649

Abstract: An integrated circuit, including: a UTBOX layer; a first cell, including: FDSOI transistors; a first STI separating the transistors; a first ground plane located beneath one of the transistors and beneath the UTBOX layer; a first well; a second cell, including: FDSOI transistors; a second STI separating the transistors; a second ground plane located beneath one of the transistors and beneath the UTBOX layer; a second well; a third STI separating the cells, reaching the bottom of the first and second wells; a deep well extending continuously beneath the first and second wells, having a portion beneath the third STI whose doping density is at least 50% higher than the doping density of the deep well beneath the first and second STIs.

Abstract translation: 一种集成电路，包括：UTBOX层; 第一个电池，包括：FDSOI晶体管; 分离晶体管的第一STI; 位于一个晶体管下方并位于UTBOX层之下的第一接地平面; 第一口井 第二个电池，包括：FDSOI晶体管; 分离晶体管的第二STI; 位于一个晶体管下方并位于UTBOX层之下的第二接地平面; 第二口井 分离细胞的第三STI，到达第一和第二孔的底部; 连续地在第一和第二阱下方延伸的深阱，具有在第三STI下面的部分，其掺杂密度比第一和第二STI下面的深井的掺杂密度高至少50％。

公开(公告)号：US20160013205A1

公开(公告)日：2016-01-14

申请号：US14771025

申请日：2013-02-28

Applicant: COMMISSARIAT À L'ÉNERGIE ATOMIQUE ET AUX ÉNERGIES ALTERNATIVES ,  INTERNATIONAL BUSINESS MACHINES CORPORATION ,  STMICROELECTRONICS, INC.

Inventor： Maud VINET ,  Kangguo CHENG ,  Bruce DORIS ,  Laurent GRENOUILLET ,  Ali KHAKIFIROOZ ,  Yannick LE TIEC ,  Qing LIU

IPC: H01L27/12 ,  H01L21/84 ,  H01L21/8238 ,  H01L29/06

CPC classification number: H01L27/12 ,  H01L21/762 ,  H01L21/823878 ,  H01L21/823892 ,  H01L21/84 ,  H01L27/1203 ,  H01L27/1207 ,  H01L29/0649 ,  H01L29/0653

Abstract: An integrated circuit, including: a first cell, including: FDSOI transistors; a UTBOX layer lying beneath the transistors; a first well lying beneath the insulator layer and beneath the transistors, the first well having a first type of doping; a first ground plane having a second type of doping, located beneath one of the transistors and between the insulator layer and the first well; a first STI separating the transistors and crossing the insulator layer; a first conductive element forming an electrical connection between the first well and the first ground plane, located under the first STI; a second cell including a second well; a second STI separating the cells, crossing the insulator layer and reaching the bottom of the first and second wells.

Abstract translation: 一种集成电路，包括：第一单元，包括：FDSOI晶体管; 位于晶体管下方的UTBOX层; 第一阱位于绝缘体层之下并位于晶体管下方，第一阱具有第一类掺杂; 具有第二类型掺杂的第一接地平面，位于所述晶体管中的一个之下且在所述绝缘体层和所述第一阱之间; 分离晶体管并与绝缘体层交叉的第一STI; 第一导电元件，其形成位于第一STI之下的第一阱和第一接地平面之间的电连接; 包括第二井的第二池; 分离所述电池的第二STI，穿过所述绝缘体层并到达所述第一和第二阱的底部。

公开(公告)号：US20150372107A1

公开(公告)日：2015-12-24

申请号：US14308014

申请日：2014-06-18

Applicant: STMicroelectronics, Inc. ,  International Business Machines Corporation ,  GLOBALFOUNDRIES Inc.

Inventor： Qing Liu ,  Xiuyu Cai ,  Ruilong Xie ,  Chun-chen Yeh ,  Kejia Wang

IPC: H01L29/66 ,  H01L29/49 ,  H01L29/78

CPC classification number: H01L27/1211 ,  H01L21/0217 ,  H01L21/02247 ,  H01L21/31111 ,  H01L27/0886 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: Methods and structures associated with forming finFETs that have fin pitches less than 30 nm are described. A selective nitridation process may be used during spacer formation on the gate to enable finer fin pitch than could be achieved using traditional spacer deposition processes. The spacer formation may also allow precise control over formation of source and drain junctions.

Abstract translation: 描述了与形成翅片间距小于30nm的finFET相关联的方法和结构。 可以在栅极上的间隔物形成期间使用选择性氮化工艺，以使得能够使用传统间隔物沉积工艺可以获得更细的翅片间距。 间隔物形成还可以允许对源极和漏极结的形成的精确控制。

公开(公告)号：US20150364578A1

公开(公告)日：2015-12-17

申请号：US14307011

申请日：2014-06-17

Applicant: STMicroelectronics, Inc. ,  International Business Machines Corporation ,  GLOBALFOUNDRIES Inc.

Inventor： Qing Liu ,  Ruilong Xie ,  Chun-chen Yeh ,  Xiuyu Cai ,  Kejia Wang

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/20

CPC classification number: H01L29/66795 ,  H01L29/20 ,  H01L29/205 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/785

Abstract: Methods and structures for forming a reduced resistance region of a finFET are described. According to some aspects, a dummy gate and first gate spacer may be formed above a fin comprising a first semiconductor composition. At least a portion of source and drain regions of the fin may be removed, and a second semiconductor composition may be formed in the source and drain regions in contact with the first semiconductor composition. A second gate spacer may be formed covering the first gate spacer. The methods may be used to form finFETs having reduced resistance at source and drain junctions.

Abstract translation: 描述了形成finFET的电阻减小区域的方法和结构。 根据一些方面，可以在包括第一半导体组合物的鳍片之上形成伪栅极和第一栅极间隔物。 可以去除鳍的源区和漏区的至少一部分，并且可以在与第一半导体组合物接触的源区和漏区中形成第二半导体组合物。 可以形成覆盖第一栅极间隔物的第二栅极间隔物。 该方法可用于形成在源极和漏极结处具有降低的电阻的finFET。

公开(公告)号：US09214429B2

公开(公告)日：2015-12-15

申请号：US14098346

申请日：2013-12-05

Applicant: STMicroelectronics, Inc. ,  International Business Machines Corporation

Inventor： John H. Zhang ,  Hsueh-Chung Chen ,  Lawrence A. Clevenger ,  Yann Mignot ,  Carl Radens ,  Richard Stephen Wise ,  Yannick Loquet ,  Yiheng Xu

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/532 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L23/53295 ,  H01L21/76807 ,  H01L21/7682 ,  H01L21/76831 ,  H01L21/76879 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/5329 ,  H01L2221/1094 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Ultra-low-k dielectric materials used as inter-layer dielectrics in high-performance integrated circuits are prone to be structurally unstable. The Young's modulus of such materials is decreased, resulting in porosity, poor film strength, cracking, and voids. An alternative dual damascene interconnect structure incorporates deep air gaps into a high modulus dielectric material to maintain structural stability while reducing capacitance between adjacent nanowires. Incorporation of a deep air gap having k=1.0 compensates for the use of a higher modulus film having a dielectric constant greater than the typical ultra-low-k (ULK) dielectric value of about 2.2. The higher modulus film containing the deep air gap is used as an insulator and a means of reducing fringe capacitance between adjacent metal lines. The dielectric layer between two adjacent metal lines thus forms a ULK/high-modulus dielectric bi-layer.

Abstract translation: 在高性能集成电路中用作层间电介质的超低k电介质材料容易在结构上不稳定。 这种材料的杨氏模量降低，导致孔隙率，差的膜强度，开裂和空隙。 一种替代的双镶嵌互连结构将深空气隙结合到高模量介电材料中以维持结构稳定性，同时减小相邻纳米线之间的电容。 结合k = 1.0的深空气间隙补偿使用介电常数大于典型的超低k（ULK）介电值约2.2的介电常数的较高模量的膜。 使用含有深空气间隙的较高模量的膜作为绝缘体和减少相邻金属线之间的条纹电容的装置。 因此，两个相邻金属线之间的电介质层形成ULK /高模量介电双层。