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公开(公告)号：US10445240B2
公开(公告)日：2019-10-15
申请号：US14450145
申请日：2014-08-01
Applicant: Analog Devices Global Unlimited Company
Inventor： Abhijit Giri , Saurbh Srivastava , Michael S. Allen
IPC: G06F12/0846
Abstract: Digital signal processors often operate on two operands per instruction, and it is desirable to retrieve both operands in one cycle. Some data caches connect to the processor over two busses and internally uses two or more memory banks to store cache lines. The allocation of cache lines to specific banks is based on the address that the cache line is associated. When two memory accesses map to the same memory bank, fetching the operands incurs extra latency because the accesses are serialized. An improved bank organization for providing conflict-free dual-data cache access—a bus-based data cache system having two data buses and two memory banks—is disclosed. Each memory bank works as a default memory bank for the corresponding data bus. As long as the two values of data being accessed belong to two separate data sets assigned to the two respective data buses, memory bank conflicts are avoided.
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公开(公告)号：US10439539B2
公开(公告)日：2019-10-08
申请号：US15135330
申请日：2016-04-21
Applicant: ANALOG DEVICES GLOBAL UNLIMITED COMPANY
Inventor： Jesus Javier Lopez , Alberto Marinas , Eduardo M. Martinez , Santiago Iriarte
IPC: H02P25/034
Abstract: The present disclosure provides a feedback control system and method for a bidirectional VCM. The system employs an analog core that is common to both the PWM and linear modes of operation. The analog core includes a feedback mechanism that determines the error in the current flowing through the motor. The feedback mechanism produces an error voltage that corresponds to the current error, and applies the voltage to a control driver. The control driver then controls the motor, based on the error voltage, in either a PWM or linear mode. By sharing a common core, the switching time between modes is improved. Furthermore, the output current error between modes is reduced.
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公开(公告)号：US10425098B2
公开(公告)日：2019-09-24
申请号：US15947222
申请日：2018-04-06
Applicant: Analog Devices Global
Inventor： Tony Yincai Liu , Dennis A. Dempsey
Abstract: Embodiments of the disclosure can provide digital-to-analog converter (DAC) termination circuits. A single or multiple parallel impedance networks can be coupled to a DAC to reduce the DAC's AC impedance, increase the DAC speed, and reduce the DAC settling time. The parallel impedance networks can be coupled to one or more of the DAC terminals in termination specific cases, or to nodes within the DAC. In an example, one-sided T-termination can be used with a single termination impedance path coupled in parallel with the DAC terminals, for reducing AC impedance at the DAC reference terminals, increasing speed, and reducing settling time. In an example, multiple impedance networks can be used in an H-bridge termination solution, which can be useful for high resolution DACs with or within a high voltage range.
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公开(公告)号：US10386324B2
公开(公告)日：2019-08-20
申请号：US15050141
申请日：2016-02-22
Applicant: Analog Devices Global
Inventor： Liam Riordan , Tudor M Vinereanu , Paul V. Errico , Dermot G. O'Keeffe , Camille L. Huin , Donal Bourke
IPC: G01N27/327 , G06K9/62 , C12Q1/00 , G06K9/52 , G01N33/487
Abstract: Subject matter herein can include identifying a biochemical test strip assembly electrically, such as using the same test circuitry as can be used to perform an electrochemical measurement, without requiring use of optical techniques. The identification can include using information about a measured susceptance of an identification feature included as a portion of the test strip assembly. The identification can be used by test circuitry to select test parameters or calibration values, or to select an appropriate test protocol for the type of test strip coupled to the test circuitry. The identification can be used by the test circuitry to validate or reject a test strip assembly, such as to inhibit use of test strips that fail meet one or more specified criteria.
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公开(公告)号：US20190245500A1
公开(公告)日：2019-08-08
申请号：US15969242
申请日：2018-05-02
Applicant: Analog Devices Global Unlimited Company
Inventor： Jonathan Ephraim David Hurwitz , Jesus Bonache , Robert Sythes , Eamonn J. Byrne
IPC: H03F3/45
Abstract: It is often desirable to distinguish between an open circuit condition and a no signal condition. In both cases an input signal may be absent, but only one of these events represents a failure of the equipment. The present disclosure provides a way to use a difference amplifier to check for open circuit events, without requiring additional circuitry at the input of the amplifier.
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Patent Agency Ranking
公开(公告)号：US20190195825A1
公开(公告)日：2019-06-27
申请号：US16329664
申请日：2017-08-29
Applicant: ANALOG DEVICES GLOBAL
Inventor： Alfonso Berduque , Helen Berney , William Allan Lane , Raymond J. Speer , Brendan Cawley , Donal McAuliffe , Patrick Martin McGuinness
IPC: G01N27/407 , G01N27/30
CPC classification number: G01N27/407 , G01N27/304
Abstract: An electrochemical sensor is provided which may be formed using micromachining techniques commonly used in the manufacture of integrated circuits. This is achieved by forming microcapillaries in a silicon substrate and forming an opening in an insulating layer to allow environmental gases to reach through to the top side of the substrate. A porous electrode is printed on the top side of the insulating layer such that the electrode is formed in the opening in the insulating layer. The sensor also comprises at least one additional electrode. The electrolyte is then formed on top of the electrodes. A cap is formed over the electrodes and electrolyte. This arrangement may easily be produced using micromachining techniques.
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公开(公告)号：US20190190370A1
公开(公告)日：2019-06-20
申请号：US15849047
申请日：2017-12-20
Applicant: Analog Devices Global Unlimited Company
Inventor： Francis Alinea Martin
CPC classification number: H02M1/4225 , G05F1/70 , H02M1/32 , H02M3/1584 , H02M3/3376 , H02M7/219 , H02M2001/0096 , H02M2003/1586
Abstract: A power factor correction device for providing tolerance to a fault condition in an input supply can include a first boost circuit, a second boost circuit, and a controller circuit. The controller circuit can interleave operation of the first boost circuit and operation of the second boost circuit such as to generate an output voltage when the input supply is received at the power factor correction device. The controller circuit can route, in response to the fault condition, a stored supply of the second boost circuit to an input of the first boost circuit. The controller circuit can control the first boost circuit to maintain the output voltage.
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公开(公告)号：US10320407B1
公开(公告)日：2019-06-11
申请号：US15890086
申请日：2018-02-06
Applicant: Analog Devices Global Unlimited Company
Inventor： Narsimh Dilip Kamath
Abstract: A system having two or more sensing nodes coupled to a control node using a serial communication channel having separate transmit and receive circuits, where each sensing node includes an ADC circuit and a microcontroller, operation of the ADC circuit in each sensing node is concurrently synchronized by the control node using the transmit circuit (e.g., with respect to the control node) of the serial communication channel. The control node can synchronize operation of two or more ADC circuits in separate sensing nodes without using shared clocks or other control signals.
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公开(公告)号：US20190173478A1
公开(公告)日：2019-06-06
申请号：US16263964
申请日：2019-01-31
Applicant: Analog Devices Global
Inventor： Sandeep Monangi , Mahesh Madhavan
Abstract: A successive approximation register analog to digital converter (SAR ADC) is provided in which impact of dielectric absorption is reduced with a correction circuit configured to adjust a present digital code value signal based at least in part upon a previous digital code value signal, an acquisition time and temperature.
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公开(公告)号：US10310539B2
公开(公告)日：2019-06-04
申请号：US15248694
申请日：2016-08-26
Applicant: Analog Devices Global
Inventor： Stefan Marinca
Abstract: The present disclosure relates to a PTAT voltage reference circuit and a temperature independent voltage reference circuit in which the effect of transistor base currents on the circuit output is compensated for. This is achieved by a pair of compensation resistors. The base current from one of the pair of transistors is used to increase the voltage drop across one of the compensation resistors. The base current from the other of the pair of transistors is used to decrease the voltage drop across another of the compensation resistors, by an equal amount. The compensation resistors are connected in series with the resistor which reflects the difference in base-emitter voltage (ΔVBE). The circuit output is measured across the series connected resistors. As such, the base currents are compensated for at the output.
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