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公开(公告)号：US10454488B1
公开(公告)日：2019-10-22
申请号：US15994112
申请日：2018-05-31
Applicant: Analog Devices Global Unlimited Company
Inventor： Sandeep Monangi
Abstract: Various examples are directed to a variable speed comparator circuit comprising a first comparator, a second comparator, and a third comparator and a logic circuit. The first comparator may be configured to generate a first comparator output using a first input and a second input. The second comparator may be configured to generate a second comparator output using the first input and the second input. The third comparator may be configured to generate a third comparator output using the first input and the second input. A propagation delay of the second comparator may be less than a propagation delay of the first comparator. Also, a propagation delay of the third comparator may be less than the propagation delay of the second comparator. The second comparator may have an input offset relative to the third comparator. The logic circuit may be configured to determine that the second comparator output and the third comparator output are not equivalent and set a comparator circuit output to the first comparator output.
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公开(公告)号：US10528070B2
公开(公告)日：2020-01-07
申请号：US15969175
申请日：2018-05-02
Applicant: Analog Devices Global Unlimited Company
Inventor： Michael C. W. Coln , Michael Mueck , Quan Wan , Sandeep Monangi
Abstract: A low-noise, low-power reference voltage circuit can include an operational transconductance amplifier (OTA) with inputs coupled to a temperature-compensated voltage, such as can be provided by source-coupled first and second field-effect transistors (FETs) having different threshold voltages. A capacitive voltage divider can feed back a portion of a reference voltage output by the OTA to the inputs of the OTA to help establish or maintain the temperature-compensated voltage across the inputs of the OTA. A switching network can be used, such as initialize the capacitive voltage divider or other capacitive feedback circuit, such as during power-down cycles, or when resuming powered-on cycles. A switch can interrupt current to the OTA during the power-down cycles to save power. The cycled voltage reference circuit can provide a reference voltage to an ADC reservoir capacitor. Powering down can occur during analog input signal sampling, during successive approximation routine (SAR) conversion, or both.
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公开(公告)号：US20190339730A1
公开(公告)日：2019-11-07
申请号：US15969175
申请日：2018-05-02
Applicant: Analog Devices Global Unlimited Company
Inventor： Michael C.W. Coln , Michael Mueck , Quan Wan , Sandeep Monangi
Abstract: A low-noise, low-power reference voltage circuit can include an operational transconductance amplifier (OTA) with inputs coupled to a temperature-compensated voltage, such as can be provided by source-coupled first and second field-effect transistors (FETs) having different threshold voltages. A capacitive voltage divider can teed back a portion of a reference voltage output by the OTA to the inputs of the OTA to help establish or maintain the temperature-compensated voltage across the inputs of the OTA. A switching network can be used, such as initialize the capacitive voltage divider or other capacitive feedback circuit, such as during power-down cycles, or when resuming powered-on cycles. A switch can interrupt current to the OTA during the power-down cycles to save power. The cycled voltage reference circuit can provide a reference voltage to an ADC reservoir capacitor. Powering down can occur during analog input signal sampling, during successive approximation routine (SAR) conversion, or both.
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公开(公告)号：US20190173478A1
公开(公告)日：2019-06-06
申请号：US16263964
申请日：2019-01-31
Applicant: Analog Devices Global
Inventor： Sandeep Monangi , Mahesh Madhavan
Abstract: A successive approximation register analog to digital converter (SAR ADC) is provided in which impact of dielectric absorption is reduced with a correction circuit configured to adjust a present digital code value signal based at least in part upon a previous digital code value signal, an acquisition time and temperature.
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公开(公告)号：US09806734B1
公开(公告)日：2017-10-31
申请号：US15343361
申请日：2016-11-04
Applicant: Analog Devices Global
Inventor： Arvind Madan , Sandeep Monangi
CPC classification number: H03M1/1245 , H03M1/0624 , H03M1/46
Abstract: A successive approximation routine (SAR) analog-to-digital converter integrated circuit can include multiple analog-to-digital converters (ADCs) sharing a reference voltage that can be perturbed by a capacitor array of a digital-to-analog converter (DAC) sampling the reference voltage, which can limit conversion accuracy. Synchronizing every bit trial across the ADCs can improve accuracy but can slow the conversion. Synchronizing a subset of at least one, but fewer than N, bit trials across ADCs can help obtain both speed and robustness. This selected subset can include bit trials corresponding to pro-defined critical events, such as those events for which a stable reference voltage node is particularly desirable.
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Patent Agency Ranking
公开(公告)号：US10122376B2
公开(公告)日：2018-11-06
申请号：US15711176
申请日：2017-09-21
Applicant: Analog Devices Global
Inventor： Anoop Manissery Kalathil , Arvind Madan , Sandeep Monangi
Abstract: Systems and methods to reduce the amount of reference current drawn by a SAR ADC by including an auxiliary or precharge reference source. The ADC can connect the bit trial capacitors of a main digital-to-analog converter (DAC) to an auxiliary or precharge reference source during the loading of the bit trials, and then the ADC can switch to a main reference buffer. After allowing enough time for both phases, the main DAC can proceed with the bit trials to resolve the remaining bits. The rest of the bit trials can be performed directly using the main reference buffer.
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公开(公告)号：US09935648B1
公开(公告)日：2018-04-03
申请号：US15692695
申请日：2017-08-31
Applicant: Analog Devices Global
Inventor： Maitrey Kamble , Arvind Madan , Sandeep Monangi
Abstract: To reduce the overall reference charge needed to perform operations, analog-to-digital converters can maintain reference voltage connections of the bit trial capacitors of the digital-to-analog converter (DAC) from the end of a current conversion to just prior to the beginning of the next acquisition phase. At the start of the next acquisition phase, the bottom plates of the bit trial capacitors of the DAC can be shorted to generate a common mode voltage. As the conversion phase begins, the bottom plates of the sampling capacitors are disconnected from the input voltage and the bottom plates of each bit trial capacitor are shorted to generate input common-mode voltage. As bit trials progress, the shorts between the bottom plates of the bit trial capacitors are removed and the bit trial results are applied to the bottom plates of the bit trial capacitors.
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公开(公告)号：US20200021305A1
公开(公告)日：2020-01-16
申请号：US16032752
申请日：2018-07-11
Applicant: Analog Devices Global Unlimited Company
Inventor： Sandeep Monangi
Abstract: A differential digital-to-analog (DAC) circuit that can include a reservoir capacitor and various switches to couple the bottom plates of the input capacitors, e.g., bit-trial capacitors, to reference voltages, e.g., REF+ or REF−. In this manner, the reservoir capacitor can be used to provide any differential charge to the input capacitors, e.g., bit-trial capacitors, and the reference voltages, e.g., REF+ and REF−, can be used to provide any common mode charge to the input capacitors.
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公开(公告)号：US10516411B1
公开(公告)日：2019-12-24
申请号：US16032752
申请日：2018-07-11
Applicant: Analog Devices Global Unlimited Company
Inventor： Sandeep Monangi
Abstract: A differential digital-to-analog (DAC) circuit that can include a reservoir capacitor and various switches to couple the bottom plates of the input capacitors, e.g., bit-trial capacitors, to reference voltages, e.g., REF+ or REF−. In this manner, the reservoir capacitor can be used to provide any differential charge to the input capacitors, e.g., bit-trial capacitors, and the reference voltages, e.g., REF+ and REF−, can be used to provide any common mode charge to the input capacitors.
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公开(公告)号：US10348319B1
公开(公告)日：2019-07-09
申请号：US15983658
申请日：2018-05-18
Applicant: Analog Devices Global Unlimited Company
Abstract: Techniques to use reservoir capacitors in ADC to supply most of the charge to bit-trial capacitors as bit-trials are performed. An accurate reference voltage source, e.g., a reference buffer circuit, only needs to supply the difference, e.g., an inaccuracy, in the charge supplied by the reservoir capacitors. Instead of having to resettle for each bit-trial, the accurate reference voltage source has only to deliver the initial charge to the reservoir capacitors during acquisition and once more when the ADC is ready to sample onto the residue amplifier. These techniques can ease the demands on the reference buffer circuit and requirement of external decoupling capacitors, for example.
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