Use of band edge gate metals as source drain contacts
    162.
    发明授权
    Use of band edge gate metals as source drain contacts 有权
    使用带边栅极金属作为源极漏极触点

    公开(公告)号:US08741753B2

    公开(公告)日:2014-06-03

    申请号:US13611736

    申请日:2012-09-12

    Abstract: A device includes a gate stack formed over a channel in a semiconductor substrate. The gate stack includes a layer of gate insulator material, a layer of gate metal overlying the layer of gate insulator material, and a layer of contact metal overlying the layer band edge gate metal. The device further includes source and drain contacts adjacent to the channel. The source and drain contacts each include a layer of the gate metal that overlies and is in direct electrical contact with a doped region of the semiconductor substrate, and a layer of contact metal that overlies the layer of gate metal.

    Abstract translation: 一种器件包括形成在半导体衬底中的沟道上方的栅叠层。 栅极堆叠包括栅极绝缘体材料层,覆盖栅极绝缘体材料层的栅极金属层和覆盖层带边缘栅极金属的接触金属层。 该装置还包括邻近通道的源极和漏极接触。 源极和漏极触点各自包括覆盖并与半导体衬底的掺杂区域直接电接触的栅极金属层以及覆盖在栅极金属层上的接触金属层。

    Electronic device having cable holding device
    163.
    发明授权
    Electronic device having cable holding device 有权
    具有电缆保持装置的电子设备

    公开(公告)号:US08735727B2

    公开(公告)日:2014-05-27

    申请号:US13326425

    申请日:2011-12-15

    CPC classification number: G06F1/181 G06F1/189 G06F2200/1639

    Abstract: An electronic device having a cable holding device is disclosed. The electronic device comprises a case; a circuit board in the case; a cable holding device attached to the circuit board and defining a through hole, a first positioning slot and a second positioning slot; the first positioning slot communicating with the through hole, and the second positioning slot communicating with the through hole; a cable electronically connected to the circuit board; wherein the cable is received either in the first positioning slot and the through hole or in the second positioning slot and the through hole.

    Abstract translation: 公开了具有电缆保持装置的电子装置。 电子设备包括壳体; 电路板在这种情况下; 连接到电路板并限定通孔的电缆固定装置,第一定位槽和第二定位槽; 所述第一定位槽与所述通孔连通,所述第二定位槽与所述通孔连通; 电缆连接到电路板的电缆; 其中所述电缆被接收在所述第一定位槽和所述通孔中或所述第二定位槽和所述通孔中。

    IDENTIFICATION OF DATA OBJECTS STORED ON CLUSTERED LOGICAL DATA CONTAINERS
    165.
    发明申请
    IDENTIFICATION OF DATA OBJECTS STORED ON CLUSTERED LOGICAL DATA CONTAINERS 审中-公开
    存储在集合逻辑数据容器上的数据对象的识别

    公开(公告)号:US20140081924A1

    公开(公告)日:2014-03-20

    申请号:US13369831

    申请日:2012-02-09

    CPC classification number: G06F16/1824

    Abstract: Exemplary embodiments provide various techniques and systems for identifying data objects stored on clustered logical data containers. In one embodiment, a method is provided for creating a backward data object handle. In this method, a request to create a file is received, and a redirector file is created on a first logical data container based on receipt of the request. A redirector handle resulting from the creation of the redirector file is received. A data object of the file is then created on a second logical data container using the redirector handle as an identifier of the data object. This redirector handle included in the identifier then becomes a backward data object handle that points from the data object to the redirector file. As such, the redirector file can be identified by referencing the identifier of the data object.

    Abstract translation: 示例性实施例提供用于识别存储在聚类逻辑数据容器上的数据对象的各种技术和系统。 在一个实施例中,提供了一种用于创建反向数据对象句柄的方法。 在该方法中,接收到创建文件的请求,并且基于接收到请求,在第一逻辑数据容器上创建重定向器文件。 接收到由重定向器文件的创建导致的重定向器句柄。 然后,使用重定向器句柄作为数据对象的标识符,在第二逻辑数据容器上创建该文件的数据对象。 标识符中包含的重定向器句柄将成为从数据对象指向重定向器文件的后向数据对象句柄。 因此,可以通过引用数据对象的标识符来识别重定向器文件。

    MOSFET integrated circuit with uniformly thin silicide layer and methods for its manufacture
    166.
    发明授权
    MOSFET integrated circuit with uniformly thin silicide layer and methods for its manufacture 有权
    具有均匀薄的硅化物层的MOSFET集成电路及其制造方法

    公开(公告)号:US08652963B2

    公开(公告)日:2014-02-18

    申请号:US13237732

    申请日:2011-09-20

    CPC classification number: H01L29/665 H01L21/28518 H01L29/6659 H01L29/7833

    Abstract: An MOSFET device having a Silicide layer of uniform thickness, and methods for its fabrication, are provided. One such method involves depositing a metal layer over wide and narrow contact trenches on the surface of a silicon semiconductor substrate. Upon formation of a uniformly thin amorphous intermixed alloy layer at the metal/silicon interface, the excess (unreacted) metal is removed. The device is annealed to facilitate the formation of a thin silicide layer on the substrate surface which exhibits uniform thickness at the bottoms of both wide and narrow contact trenches.

    Abstract translation: 提供具有均匀厚度的硅化物层的MOSFET器件及其制造方法。 一种这样的方法包括在硅半导体衬底的表面上的宽且窄的接触沟槽上沉积金属层。 在金属/硅界面处形成均匀薄的无定形混合合金层时,除去过量的(未反应的)金属。 该器件被退火以促进在衬底表面上形成薄的硅化物层,其在宽和窄接触沟槽的底部显示均匀的厚度。

    WATERMARKING IMAGE BLOCK DIVISION METHOD AND DEVICE FOR WESTERN LANGUAGE WATERMARKING PROCESSING
    167.
    发明申请
    WATERMARKING IMAGE BLOCK DIVISION METHOD AND DEVICE FOR WESTERN LANGUAGE WATERMARKING PROCESSING 有权
    WATERMARKING图像块分割方法和西语言水印处理装置

    公开(公告)号:US20140003649A1

    公开(公告)日:2014-01-02

    申请号:US13997258

    申请日:2011-12-23

    Abstract: The application provides a method for partitioning a watermark image with western language characters, comprising: partitioning a western language characters image along rows and columns to form a plurality of character image blocks; identifying valid character image blocks from the formed character image blocks; counting sizes of the valid character image blocks to determine if the image corresponds to a document with a large font size or a document with a small font size; dividing words in the image into a plurality of groups, wherein each divided group in the document with large font size has different numbers of words from that with small font size; and dividing equally the divided word groups into multiple portions corresponding to watermark image blocks. The application further provides a device for partitioning a watermark image with western language characters. The operability of watermark embedding process can be ensured through the above technical solution.

    Abstract translation: 该应用程序提供了一种用于用西方语言字符分割水印图像的方法,包括:沿着行和列划分西方语言字符图像以形成多个字符图像块; 从形成的字符图像块中识别有效的字符图像块; 计算有效字符图像块的大小,以确定图像是否对应于具有较大字体大小的文档或具有小字体大小的文档; 将图像中的单词划分成多个组,其中具有大字体大小的文档中的每个划分组具有与具有小字体尺寸的单词不同的字数; 并将划分的字组分成相当于水印图像块的多个部分。 该应用还提供了一种用于用西语字符分割水印图像的设备。 通过上述技术方案可以确保水印嵌入过程的可操作性。

    ETSOI with reduced extension resistance
    168.
    发明授权
    ETSOI with reduced extension resistance 有权
    ETSOI具有降低的延伸电阻

    公开(公告)号:US08518758B2

    公开(公告)日:2013-08-27

    申请号:US12726889

    申请日:2010-03-18

    Inventor: Bin Yang Man Fai Ng

    Abstract: A semiconductor is formed on an SOI substrate, such as an extremely thin SOI (ETSOI) substrate, with increased extension thickness. Embodiments include semiconductor devices having an epitaxially formed silicon-containing layer, such as embedded silicon germanium (eSiGe), on the SOI substrate. An embodiment includes forming an SOI substrate, epitaxially forming a silicon-containing layer on the SOI substrate, and forming a gate electrode on the epitaxially formed silicon-containing layer. After gate spacers and source/drain regions are formed, the gate electrode and underlying silicon-containing layer are removed and replaced with a high-k metal gate. The use of an epitaxially formed silicon-containing layer reduces SOI thickness loss due to fabrication process erosion, thereby increasing extension thickness and lowering extension resistance.

    Abstract translation: 在诸如极薄的SOI(ETSOI)衬底的SOI衬底上形成半导体,具有增加的延伸厚度。 实施例包括在SOI衬底上具有外延形成的含硅层(例如嵌入硅锗(eSiGe))的半导体器件。 实施例包括形成SOI衬底,在SOI衬底上外延形成含硅层,并在外延形成的含硅层上形成栅电极。 在形成栅极间隔物和源极/漏极区之后,去除栅电极和下面的含硅层,并用高k金属栅极代替。 使用外延形成的含硅层由于制造工艺侵蚀而减少SOI厚度损失,从而增加延伸厚度并降低延伸电阻。

    CALIBRATION APPARATUS FOR PERFORMING PHASE DETECTION/EDGE DISTANCE DETECTION UPON SIGNALS AND RELATED CALIBRATION METHOD THEREOF
    170.
    发明申请
    CALIBRATION APPARATUS FOR PERFORMING PHASE DETECTION/EDGE DISTANCE DETECTION UPON SIGNALS AND RELATED CALIBRATION METHOD THEREOF 审中-公开
    用于执行信号相位检测/边缘距离检测的校准装置及其相关校准方法

    公开(公告)号:US20130099835A1

    公开(公告)日:2013-04-25

    申请号:US13280341

    申请日:2011-10-25

    CPC classification number: G11B7/126 G11B20/10222 G11B2220/2537 H03K5/26

    Abstract: An exemplary calibration apparatus includes a detecting circuit and a calibrating circuit. The detecting circuit is arranged for generating a detection result by detecting relationship between edges of a plurality of signals generated from a plurality of signal sources, wherein at least one of the edges is a falling edge. The calibrating circuit is coupled to the detecting circuit, and arranged for calibrating at least one of the signal sources according to the detection result. An exemplary calibration method includes the following steps: generating a detection result by detecting relationship between edges of a plurality of signals generated from a plurality of signal sources, wherein at least one of the edges is a falling edge; and calibrating at least one of the signal sources according to the detection result.

    Abstract translation: 示例性的校准装置包括检测电路和校准电路。 检测电路被布置成通过检测从多个信号源产生的多个信号的边缘之间的关系来产生检测结果,其中至少一个边缘是下降沿。 校准电路耦合到检测电路,并被安排用于根据检测结果校准至少一个信号源。 示例性校准方法包括以下步骤:通过检测从多个信号源产生的多个信号的边缘之间的关系来产生检测结果,其中至少一个边缘是下降沿; 并根据检测结果校准至少一个信号源。

Patent Agency Ranking