-
公开(公告)号：US11178473B1
公开(公告)日：2021-11-16
申请号：US16894611
申请日：2020-06-05
Applicant: INPHI CORPORATION
Inventor： Radhakrishnan L. Nagarajan , Liang Ding , Mark Patterson , Roberto Coccioli , Steve Aboagye
Abstract: A co-packaged optical-electrical module includes a module substrate with a minimum lateral dimension no greater than 100 mm. The co-packaged optical-electrical module further includes a main die with a processor chip disposed at a central region of the module substrate, the processor chip being configured to operate with a digital-signal processing (DSP) interface for extra-short-reach data interconnect. Additionally, the co-packaged optical-electrical module includes a plurality of chiplet dies disposed densely along a peripheral region of the module substrate. Each chiplet die is configured to be self-packaged light engine on a sub-module substrate with a minimum lateral dimension to allow a maximum number of chiplet dies on the module substrate with a distance of any chiplet die from the main die smaller than 50 mm for extra-short-reach interconnect operation.
-
公开(公告)号：US20210336761A1
公开(公告)日：2021-10-28
申请号：US16860403
申请日：2020-04-28
Applicant: INPHI CORPORATION
Inventor： Benjamin P. SMITH , Jamal RIANI
Abstract: The present invention is directed to circuits and communication. More specifically, a specific embodiment of the present invention provides a timing recovery device with two stages. The first stage generates a clock signal to sample the received waveform, and the second stage provides timing-jitter mitigation. The second stage includes a jitter mitigation circuit with coefficients a function of the instantaneous jitter estimate, in addition to a jitter estimation tracking loop consisting of an error generator, a timing error detector and a loop filter to compensate for timing jitter associated with the clock signal. There are other embodiments as well.
-
163.发明申请公开(公告)号：US20210306009A1
公开(公告)日：2021-09-30
申请号：US17347315
申请日：2021-06-14
Applicant: INPHI CORPORATION
Inventor： Jamal RIANI , Farshid RAD , Benjamin P. SMITH , Yu LIAO , Sudeep BHOJA
Abstract: The present invention is directed to data communication. More specifically, an embodiment of the present invention provides an error correction system. Input data signals are processed by a feedforward equalization module and a decision feedback back equalization module. Decisions generated by the decision feedback equalization module are processed by an error detection module, which determines error events associated with the decisions. The error detection module implements a reduced state trellis path. There are other embodiments as well.
-
164.发明申请公开(公告)号：US20210297294A1
公开(公告)日：2021-09-23
申请号：US17224835
申请日：2021-04-07
Applicant: INPHI CORPORATION
Inventor： Dragos CARTINA , Ankit BHARGAV , Jamal RIANI , Wen-Sin LIEW , Yu LIAO , Chang-Feng LOI
Abstract: A device and method of operation for digital compensation of dynamic distortion. The transmitter device includes at least a digital-to-analog converter (DAC) connected to a lookup table (LUT), a first shift register, and a second shift register. The method includes iteratively adjusting the input values via the LUT to induce changes in the DAC output that compensate for dynamic distortion, which depends on precursors, current cursors, and postcursors. More specifically, the method includes producing and capturing average output values for each possible sequence of three symbols using the shift register and LUT configuration. Then, the LUT is updated with estimated values to induce desired output values that are adjusted to eliminate clipping. These steps are performed iteratively until one or more check conditions are satisfied. This method can also be combined with techniques such as equalization, eye modulation, and amplitude scaling to introduce desirable output signal characteristics.
-
公开(公告)号：US20210288672A1
公开(公告)日：2021-09-16
申请号：US16818864
申请日：2020-03-13
Applicant: INPHI CORPORATION
Inventor： Benjamin SMITH , Volodymyr SHVYDUN , Jamal RIANI , ILya LYUBOMIRSKY
Abstract: The present invention is directed to data communication and encoding techniques. More specifically, an embodiment of the present invention provides a communication device that aligns a data stream with RS symbols. An interleaver interleaves RS symbols to generate an interleaved RS symbol data stream. Hamming parity blocks are generated for corresponding groups of RS symbols and inserted into the interleaved RS symbol data stream. There are other embodiments as well.
-
Patent Agency Ranking
公开(公告)号：US11121955B2
公开(公告)日：2021-09-14
申请号：US16848597
申请日：2020-04-14
Applicant: INPHI CORPORATION
Inventor： Jamal Riani , Arash Farhoodfar , Sudeep Bhoja , Tarun Setya
Abstract: A data communication device includes a host receive section for receiving incoming host data from a host device. The host receive section includes a plurality of host receive lanes. A host transmit section for transmitting outgoing host data to the host device includes a plurality of host transmit lanes and a host cross point section. A line receive section for receiving incoming line data from a line device includes a plurality of line receive lanes. A line transmit section for transmitting outing line data to the line device includes a plurality of line transmit lanes and a line cross point section. A link monitor section coupled to the host transmit section and the line receive section is configured to detect errors between the host transmit section and the line receive section.
-
公开(公告)号：US20210280349A1
公开(公告)日：2021-09-09
申请号：US17096419
申请日：2020-11-12
Applicant: INPHI CORPORATION
Inventor： Marco GARAMPAZZI , Matteo PISATI
Abstract: The present invention is directed to electrical circuits. and more specially, inductor designs that reduce on-chip electromagnetic coupling in certain applications. In a specific embodiment, the present invention provides an inductor that includes coils that are configured to generate magnetic fields of opposite polarities. The electromagnetic fields generated by the inductor coils substantially cancel out with each other, thereby minimizing parasitic inductance of the inductor and reducing interference with operations of other components in an integrated circuit. There are other embodiments as well.
-
公开(公告)号：US11109515B1
公开(公告)日：2021-08-31
申请号：US16894639
申请日：2020-06-05
Applicant: INPHI CORPORATION
Inventor： Radhakrishnan L. Nagarajan , Liang Ding , Mark Patterson , Roberto Coccioli , Steve Aboagye
Abstract: An integrated heatsink for a co-packaged optical-electrical module includes a base plate attached on top of a co-packaged optical-electrical module. The integrated heatsink further includes a plurality of fin structures extended upward from the base plate except a central cavity region with missing sections of fins, each fin extended along an axial direction from a front edge to a back edge of the base plate except some trenches shallow in depth across some fin structures and some other trenches deep in depth down to the base plate either along or across some fin structures. Additionally, the integrated heatsink includes multiple heat pipes including shaped portions embedded in the trenches in the plurality of fin structures. At least one bottom horizontal portion per heat pipe is brazed to the base plate in a corresponding region that is superimposed on hot spots of the co-packaged optical-electrical module under the base plate.
-
公开(公告)号：US20210265805A1
公开(公告)日：2021-08-26
申请号：US17169037
申请日：2021-02-05
Applicant: INPHI CORPORATION
Inventor： Xiaoguang HE , Radhakrishnan L. NAGARAJAN
Abstract: A light source based on integrated silicon photonics includes a die of a silicon substrate having at least one chip site configured with a surface region, a trench region, and a first stopper region located separately between the surface region and the trench region. The trench region is configured to be a depth lower than the surface region. The light source includes a laser diode chip having a p-side facing the chip site and a n-side being distal to the chip site. The p-side includes a gain region bonded to the trench region, an electrode region bonded to the surface region, and an isolation region engaged with the stopper region to isolate the gain region from the electrode region. The light source also includes a conductor layer in the die configured to connect the gain region to an anode electrode and separately connect the electrode region to a cathode electrode.
-
公开(公告)号：US20210152255A1
公开(公告)日：2021-05-20
申请号：US17162884
申请日：2021-01-29
Applicant: INPHI CORPORATION
Inventor： Mario R. HUEDA , Oscar E. AGAZZI
Abstract: A method and structure for a coherent optical receiver device. Timing recovery (TR) is implemented after channel dispersion (i.e., chromatic dispersion (CD) and polarization mode dispersion (PMD)) compensation blocks. This architecture provides both improves performance and reduces power consumption of the device. Also, a TR loop is provided, enabling computing, by an error evaluation module, a first sampling phase error (SPE) and computing, by a timing phase information (TPI) module coupled to the error evaluation module, a second SPE from a plurality of CD equalizer taps PMD equalizer taps. The first and second SPE are combined into a total phase error (TPE) in a combining module, and the resulting TPE is filtered by a timing recovery (TR) filter coupled to an interpolated timing recovery (ITR) module and the combining module. The ITR module then synchronizes an input signal of the coherent optical receiver according to the TPE.
-
-
-
-
-
-
-
-
-
Search Results
836
records
(took 0.022 seconds)
