公开(公告)号：US20230268830A1

公开(公告)日：2023-08-24

申请号：US18310824

申请日：2023-05-02

Applicant: STMicroelectronics S.r.I.

Inventor： Edoardo Botti

IPC: H02M3/155 ,  H03F3/217 ,  H04R3/04

CPC classification number: H02M3/155 ,  H03F3/217 ,  H04R3/04 ,  H03F2200/03

Abstract: An audio electronic system includes a DC switching converter comprising first and second Zeta converters, each comprising an input stage, an output stage, a first switching stage, and a second switching stage. The input stage of each Zeta converter comprises a respective input inductor having a first terminal electrically coupled to the respective first switching stage. The input inductors of the input stages of the first and second Zeta converters are magnetically coupled in such a way that when current enters the terminal of the input inductor of the first Zeta converter that is coupled to the first switch stage of the first Zeta converter, a voltage induced by the coupled current is positive at the terminal of the input inductor of the second Zeta converter that is coupled to the first switching stage of the second Zeta converter.

公开(公告)号：US11716579B2

公开(公告)日：2023-08-01

申请号：US17735048

申请日：2022-05-02

Applicant: STMICROELECTRONICS S.r.I.

Inventor： Marco Veneri ,  Alessandro Morcelli

IPC: H04R19/04 ,  H04R23/00 ,  H04R3/06 ,  H04R1/04 ,  H04R3/00 ,  H04R19/00 ,  G10L25/78

CPC classification number: H04R23/00 ,  H04R1/04 ,  H04R3/00 ,  H04R3/06 ,  H04R19/005 ,  H04R19/04 ,  H04R23/006 ,  G10L25/78 ,  H04R2201/003

Abstract: Described herein is a MEMS acoustic transducer device provided with a micromechanical detection structure that detects acoustic-pressure waves and supplies a transduced electrical quantity, and with an integrated circuit operatively coupled to the micromechanical detection structure and having a reading module that generates at output an audio signal as a function of the transduced electrical quantity. The integrated circuit is further provided with a recognition module, which recognizes a of sound activity event associated to the transduced electrical quantity. The MEMS acoustic transducer has an output that supplies at output a data signal that carries information regarding recognition of the sound activity event.

公开(公告)号：US11699956B2

公开(公告)日：2023-07-11

申请号：US17989877

申请日：2022-11-18

Applicant: STMicroelectronics S.r.I.

Inventor： Claudio Adragna ,  Francesco Ferrazza

IPC: H02M3/335 ,  H02M1/08

CPC classification number: H02M3/33569 ,  H02M1/08

Abstract: In an embodiment, a method for operating an ACF converter includes: turning on a low-side transistor that is coupled between a primary winding of a transformer and a reference terminal to cause a forward current to enter the primary winding, turning off the low-side transistor; after turning off the low-side transistor, turning on a high-side transistor that is coupled between the primary winding and a clamp capacitor to cause a reverse current to flow through the primary winding; and after turning on the high-side transistor, when an overcurrent of the reverse current is not detected, keeping the high-side transistor on for a first period of time, and turning off the high-side transistor after the first period of time, and when the overcurrent of the reverse current is detected, turning off the high-side transistor without keeping the high-side transistor on for the first period of time.

公开(公告)号：US20230170914A1

公开(公告)日：2023-06-01

申请号：US18054333

申请日：2022-11-10

Applicant: STMicroelectronics S.r.I.

Inventor： Agatino Massimo Maccarrone ,  Antonino Conte ,  Francesco Tomaiuolo ,  Michelangelo Pisasale ,  Marco Ruta

IPC: H03M1/06

CPC classification number: H03M1/0604

Abstract: In accordance with an embodiment, a digital-to-analog converter (DAC) includes: a W-2W current mirror that includes a first plurality of MOS transistors having a first width, and second plurality of MOS transistors having a second width that is twice the first width, where ones of the second plurality of MOS transistors are coupled between drains of adjacent ones of the first plurality of MOS transistors; and a bulk bias generator having a plurality of output nodes coupled to corresponding bulk nodes of the first plurality of MOS transistors, wherein the plurality of output nodes are configured to provide voltages that are inversely proportional to temperature.

公开(公告)号：US20230141001A1

公开(公告)日：2023-05-11

申请号：US17989877

申请日：2022-11-18

Applicant: STMicroelectronics S.r.I.

Inventor： Claudio Adragna ,  Francesco Ferrazza

IPC: H02M3/335 ,  H02M1/08

CPC classification number: H02M3/33569 ,  H02M1/08

Abstract: In an embodiment, a method for operating an ACF converter includes: turning on a low-side transistor that is coupled between a primary winding of a transformer and a reference terminal to cause a forward current to enter the primary winding, turning off the low-side transistor; after turning off the low-side transistor, turning on a high-side transistor that is coupled between the primary winding and a clamp capacitor to cause a reverse current to flow through the primary winding; and after turning on the high-side transistor, when an overcurrent of the reverse current is not detected, keeping the high-side transistor on for a first period of time, and turning off the high-side transistor after the first period of time, and when the overcurrent of the reverse current is detected, turning off the high-side transistor without keeping the high-side transistor on for the first period of time.

公开(公告)号：US20230006546A1

公开(公告)日：2023-01-05

申请号：US17364147

申请日：2021-06-30

Applicant: STMicroelectronics S.r.I.

Inventor： Juri Giovannone ,  Valeria Bottarel ,  Stefano Corona

IPC: H02M3/04 ,  H03K5/24

Abstract: A direct current (DC) to DC (DC-DC) converter includes a comparator setting a pulse width of a signal pulse, the pulse width corresponding to a voltage level of an output voltage of the DC-DC converter; a digital delay line (DDL) operatively coupled to the comparator, the DDL adjusting the pulse width of the signal pulse by linearly introducing delays to the signal pulse; a multiplexer operatively coupled to the DDL, the multiplexer selectively outputting a delayed version of the signal pulse; a phase detector operatively coupled to a system clock and the multiplexer, the phase detector generating a phase error between an output of the multiplexer and the system clock; and a logic control circuit operatively coupled to the multiplexer and the DDL, the logic control circuit adjusting the delay introduced to the signal pulse in accordance with the phase error.

公开(公告)号：US20220229887A1

公开(公告)日：2022-07-21

申请号：US17646981

申请日：2022-01-04

Applicant: STMicroelectronics S.r.I.

Inventor： Enrico Rosario Alessi ,  Simone Ferri ,  Fabio Passaniti

IPC: G06F21/31 ,  G06F3/041 ,  H04R1/08 ,  G01P13/00

Abstract: To recognize an authorized user from an unauthorized user of a portable electronic apparatus, the portable electronic apparatus has a plurality of sensors and a user-recognition circuit. The sensors are each configured to generate a signal representative of a respective physical quantity associated with the use, by a user, of the portable electronic apparatus in an operating state. The user-recognition circuit is configured to receive a plurality of electrical signals from the plurality of sensors; determine a plurality of recognition parameters, each associated with a specific mode of use of the portable electronic apparatus by the user; determine a plurality of indicators of use, one for each recognition parameter, wherein each parameter indicates the probability that, at a time instant, the respective recognition parameter is associable with an unauthorized user; determine a probability of intrusion from the plurality of indicators of use; and compare the probability of intrusion with an intrusion threshold.

公开(公告)号：US20220188610A1

公开(公告)日：2022-06-16

申请号：US17455770

申请日：2021-11-19

Applicant: STMicroelectronics S.r.I. ,  STMicroelectronics (Rousset) SAS

Inventor： Laurent Folliot ,  Mirko Falchetto ,  Pierre Demaj

IPC: G06N3/063 ,  G06N3/04 ,  G06F12/02

Abstract: According to an aspect, a method is proposed for defining placements, in a volatile memory, of temporary scratch buffers used during an execution of an artificial neural network, the method comprising: determining an execution order of layers of the neural network, defining placements, in a heap memory zone of the volatile memory, of intermediate result buffers generated by each layer, according to the execution order of the layers, determining at least one free area of the heap memory zone over the execution of the layers, defining placements of temporary scratch buffers in the at least one free area of the heap memory zone according to the execution order of the layers.

公开(公告)号：US20220013984A1

公开(公告)日：2022-01-13

申请号：US17360381

申请日：2021-06-28

Applicant: STMicroelectronics (Rousset) SAS ,  STMicroelectronics S.r.I.

Inventor： Romeo Letor ,  Vanni Poletto ,  Antoine Pavlin ,  Nadia Lecci ,  Alfio Russo

IPC: H01S5/062 ,  H01S5/026 ,  H03K5/07

Abstract: An embodiment pulse generator circuit comprises a first electronic switch coupled between first and second nodes, and a second electronic switch coupled between the second node and a reference node. An LC resonant circuit comprising an inductance and a capacitance is coupled between the first and reference nodes along with charge circuitry comprises a further inductance in a current flow line between a supply node and an intermediate node in the LC resonant circuit. Drive circuitry of the electronic switches repeats, during a sequence of switching cycles, charge time intervals, wherein the capacitance in the LC resonant circuit is charged via the charge circuit, and pulse generation time intervals, wherein a pulsed current is provided to the load via the first and second nodes. The charge and pulse generation time intervals are interleaved with oscillation time intervals where the LC resonant circuit oscillates at a resonance frequency.

公开(公告)号：US20210357538A1

公开(公告)日：2021-11-18

申请号：US17443497

申请日：2021-07-27

Applicant: STMicroelectronics S.r.I. ,  STMicroelectronics Application GMBH

Inventor： Roberto Colombo ,  Nicolas Bernard Grossier ,  Giovanni Disirio

IPC: G06F21/83 ,  G06F21/64 ,  G06F12/02 ,  G06F9/38 ,  G06F9/445 ,  H04L9/32 ,  G06F21/57 ,  G09C1/00 ,  G06F21/74 ,  H04W12/106

Abstract: A hardware secure element includes a processing unit and a receiver circuit configured to receive data comprising a command field and a parameter field adapted to contain a plurality of parameters. The hardware secure element also includes at least one hardware parameter check module configured to receive at an input a parameter to be processed selected from the plurality of parameters, and to process the parameter to be processed to verify whether the parameter has given characteristics. The hardware parameter check module has associated one or more look-up tables configured to receive at an input the command field and a parameter index identifying the parameter to be processed by the hardware parameter check module, and to determine for the command field and the parameter index a configuration data element.