公开(公告)号：US20130251373A1

公开(公告)日：2013-09-26

申请号：US13785475

申请日：2013-03-05

Applicant: SEIKO INSTRUMENTS INC.

Inventor： Hironori YANO ,  Fumiyasu UTSUNOMIYA

IPC: G08C23/04

CPC classification number: G08C23/04

Abstract: The device identification apparatus includes: a remote controller signal detecting section for detecting an optical signal from a remote controller; a receiving section for receiving the optical signal from the remote controller; a signal decryption section for decrypting the optical signal received by the receiving section; and a transmitting section for transmitting a device identification signal when the optical signal is a device selecting signal, and configured such that operations of the receiving section, the signal decryption section, and the transmitting section are started in response to a detecting signal of the remote controller signal detecting section, thereby realizing a device identification apparatus in which power consumption during standby is minimized.

Abstract translation: 装置识别装置包括：遥控器信号检测部分，用于检测来自遥控器的光信号; 接收部分，用于从遥控器接收光信号; 信号解密部分，用于解密由接收部分接收的光信号; 以及发送部，用于当光信号是设备选择信号时发送设备识别信号，并且被配置为使得接收部分，信号解密部分和发送部分的操作响应于远端的检测信号而启动 控制器信号检测部分，从而实现其中待机期间的功耗最小化的装置识别装置。

公开(公告)号：US20130249473A1

公开(公告)日：2013-09-26

申请号：US13784184

申请日：2013-03-04

Applicant: SEIKO INSTRUMENTS INC.

Inventor： Makoto MITANI ,  Kotaro WATANABE

IPC: H02J7/00

CPC classification number: H02J7/0031 ,  H02J2007/0037

Abstract: The semiconductor device includes the charging system including: electric power generating unit for supplying electric power; electric power storing unit for storing electric power generated by the electric power generating unit; switch unit provided in a charging path for charging the electric power storing unit with the electric power generated by the electric power generating unit; a comparator driven by the electric power generated by the electric power generating unit for comparing a reference voltage and a stored voltage of the electric power storing unit; and a level converter provided between the comparator and the switch unit for, based on a result of a comparison made by the comparator, converting a level of a generated voltage to a level of the stored voltage and outputting a resultant to the switch unit.

Abstract translation: 该半导体装置包括：充电系统，包括：用于供电的发电单元; 蓄电单元，用于存储由所述发电单元产生的电力; 开关单元，设置在充电路径中，用于利用所述发电单元产生的电力对所述蓄电单元进行充电; 由所述发电单元产生的用于比较所述电力存储单元的参考电压和存储电压的电力驱动的比较器; 以及电平转换器，其设置在所述比较器和所述开关单元之间，用于基于由所述比较器进行的比较的结果，将所产生的电压的电平转换为所存储的电压的电平，并将结果输出到所述开关单元。

公开(公告)号：US20130242710A1

公开(公告)日：2013-09-19

申请号：US13837097

申请日：2013-03-15

Applicant: SEIKO INSTRUMENTS INC.

Inventor： Daishi ARIMATSU

IPC: H01L41/047 ,  G04R60/00 ,  H03B1/00

CPC classification number: H01L41/0475 ,  G04R60/00 ,  G04R60/08 ,  H01L41/0477 ,  H03B1/00 ,  H03H9/1007 ,  H03H9/132 ,  H03H9/21 ,  H03H2003/026

Abstract: There is provided a piezoelectric vibrating piece including: a piezoelectric plate that includes a pair of vibrating arm portions, and a base portion which integrally fixes the base end portions of the pair of vibrating arm portions along a length direction; excitation electrodes which are formed on the vibrating arm portions and vibrate the vibrating arm portions; mounting electrodes which are formed on the base portion and mount the piezoelectric plate on external portions using a joining member; and leading-out electrodes which connect the excitation electrodes and the mounting electrodes, in which the leading-out electrodes are formed by folding back several times between the excitation electrodes and the mounting electrodes.

Abstract translation: 提供了一种压电振动片，其包括：压电板，其包括一对振动臂部;以及基部，其沿着长度方向一体地固定所述一对振动臂部的基端部; 励磁电极，其形成在所述振动臂部上并振动所述振动臂部; 安装电极，其形成在基部上并使用接合部件将压电板安装在外部; 以及连接激励电极和安装电极的引出电极，其中通过在激励电极和安装电极之间折回多次形成引出电极。

公开(公告)号：US20130234687A1

公开(公告)日：2013-09-12

申请号：US13779197

申请日：2013-02-27

Applicant: SEIKO INSTRUMENTS INC.

Inventor： Manabu FUJIMURA ,  Takashi IMURA ,  Yuji KOBAYASHI

IPC: G05F1/10

CPC classification number: G05F1/10 ,  G05F1/575

Abstract: Provided is a voltage regulator having improved transient response characteristics even when a load current is switched from a light load to a heavy load. The voltage regulator includes, to a gate of a detection transistor constituting an output current detection circuit: a resistive element for interrupting the gate of the detection transistor from an output terminal of a differential amplifier circuit in an AC manner; and a capacitive element connected to an output terminal of the voltage regulator in an AC manner.

Abstract translation: 提供即使当负载电流从轻负载切换到重负载时，也具有改善的瞬态响应特性的电压调节器。 电压调节器包括构成输出电流检测电路的检测晶体管的栅极：用于以AC方式从差分放大器电路的输出端中断检测晶体管的栅极的电阻元件; 以及以AC方式连接到电压调节器的输出端子的电容元件。

公开(公告)号：US20130226281A1

公开(公告)日：2013-08-29

申请号：US13772096

申请日：2013-02-20

Applicant: SEIKO INSTRUMENTS INC. ,  TOHOKU UNIVERSITY

Inventor： Akihiko CHIBA ,  Shingo KUROSU ,  Yasunori AKASAKA ,  Tomoo KOBAYASHI ,  Ryo SUGAWARA

IPC: A61F2/07 ,  A61F2/82

CPC classification number: A61F2/07 ,  A61F2/82 ,  A61L31/022 ,  C22C19/07 ,  C22F1/10

Abstract: Provided is a Co-based alloy for a living body based on Co—Cr—W—Fe, including a composition of Cr: 5% by mass to 30% by mass, W: 5% by mass to 20% by mass, Fe: 1% by mass to 15% by mass, Co as the remainder, and unavoidable impurities. In this alloy, when the content of W is 5% by mass to 10% by mass, the content of Fe can be set to be in a range of 1% by mass to 5% by mass, and when the content of W is 11% by mass to 20% by mass, the content of Fe can be set to be in a range of 3% by mass to 15% by mass.

Abstract translation: 本发明提供一种基于Co-Cr-W-Fe的生物体用Co系合金，其组成为：Cr：5质量％〜30质量％，W：5质量％〜20质量％，Fe ：1质量％〜15质量％，余量为Co，不可避免的杂质。 在该合金中，当W的含量为5质量％〜10质量％时，Fe的含量可以设定为1质量％〜5质量％的范围，W的含量 11质量％〜20质量％，Fe的含量可以设定在3质量％〜15质量％的范围。

公开(公告)号：US20130221432A1

公开(公告)日：2013-08-29

申请号：US13761304

申请日：2013-02-07

Applicant: Seiko Instruments Inc.

Inventor： Yukimasa MINAMI

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/7813 ,  H01L21/26586 ,  H01L29/0623 ,  H01L29/0634 ,  H01L29/0878 ,  H01L29/0886 ,  H01L29/66734 ,  H01L29/7809

Abstract: Provided is a semiconductor device having a vertical MOS transistor and a method of manufacturing the same. The vertical MOS transistor has a trench gate, a distance between a gate electrode and an N-type high concentration buried layer below the gate electrode is formed longer than that in the conventional structure, and a P-type trench bottom surface lower region (5) is formed therebetween. In this manner, when a high voltage is applied to a drain region and 0 V is applied to the gate electrode, the trench bottom surface lower region (5) is depleted, thereby increasing the breakdown voltage in the OFF state.

Abstract translation: 提供一种具有垂直MOS晶体管的半导体器件及其制造方法。 垂直MOS晶体管具有沟槽栅极，栅极电极和栅电极下方的N型高浓度掩埋层之间的距离比常规结构形成得更长，并且P型沟槽底面下部区域（5 ）。 以这种方式，当向漏极区域施加高电压并且向栅电极施加0V时，沟槽底表面下部区域（5）被耗尽，从而在断开状态下增加击穿电压。

公开(公告)号：US20130207633A1

公开(公告)日：2013-08-15

申请号：US13761868

申请日：2013-02-07

Applicant: SEIKO INSTRUMENTS INC.

Inventor： Michiyasu DEGUCHI

IPC: G05F1/625

CPC classification number: G05F1/625 ,  H02M1/32 ,  H02M3/156 ,  H02M2001/0006

Abstract: Provided is a switching regulator including a circuit for detecting a short-circuit state easily and reliably, without the need of an adjustment step such as trimming. In accordance with a drive signal of a power switching element of the switching regulator, a discharge circuit is controlled. When the power switching element is short-circuited and becomes the ON state all the time, the discharge circuit stops its operation, and a capacitor is continuously charged. A voltage detection circuit detects that a charge voltage of the capacitor has reached a predetermined potential, to thereby detect the short-circuit state.

Abstract translation: 提供了一种开关调节器，其包括用于容易且可靠地检测短路状态的电路，而不需要诸如修整的调整步骤。 根据开关调节器的功率开关元件的驱动信号，控制放电电路。 当功率开关元件短路并且始终变为导通状态时，放电电路停止工作，电容器连续充电。 电压检测电路检测电容器的充电电压已经达到预定电位，从而检测短路状态。

公开(公告)号：US20130194897A1

公开(公告)日：2013-08-01

申请号：US13738066

申请日：2013-01-10

Applicant: SEIKO INSTRUMENTS INC.

Inventor： Kazuo KATO ,  Akira TAKAKURA ,  Tomohiro IHASHI ,  Takanori HASEGAWA ,  Toshitaka FUKUSHIMA

IPC: G04G19/00

CPC classification number: G04G19/00 ,  G04B99/00

Abstract: There is provided an electronic timepiece of the invention that includes a solar panel which receives light to generate electric power, is operated with the electric power supplied from a secondary battery charged with an electromotive voltage of the solar panel, and stops a display operation of a display unit with transition to a power saving mode under predetermined conditions, the electronic timepiece including a control unit (mode control unit) which avoids transition from the normal mode to the power saving mode, when a voltage of the secondary battery is equal to or more than a predetermined voltage value.

Abstract translation: 提供了一种本发明的电子表，其包括接收光以产生电力的太阳能电池板，利用从充电了太阳能电池板的电动势的二次电池供给的电力进行动作，停止显示操作 显示单元，其在预定条件下转换到省电模式，所述电子钟表包括控制单元（模式控制单元），当所述二次电池的电压等于或等于所述电子表时，所述控制单元（模式控制单元）避免从正常模式转换到省电模式 超过预定的电压值。

公开(公告)号：US20130188425A1

公开(公告)日：2013-07-25

申请号：US13746859

申请日：2013-01-22

Applicant: Seiko Instruments, Inc.

Inventor： Yutaka SATO

IPC: G11C16/26

CPC classification number: G11C16/26 ,  G11C16/28

Abstract: Provided is a readout circuit for a non-volatile memory device, which has a large readout margin for distinguishing between 0 and 1 of data and has a small circuit area. A voltage output from a single bias circuit is applied to a gate of a memory element and a gate of an NMOS transistor serving as a reference current source to be compared with a current flowing through the memory element. Thus, the gates are controlled by the same voltage, and hence characteristics fluctuations in the operating temperature range and the operating power supply voltage range are reduced. Therefore, a large readout margin for distinguishing 0 and 1 of data can be obtained, resulting in a simplified circuit configuration.

Abstract translation: 提供一种用于非易失性存储器件的读出电路，其具有用于区分数据的0和1之间的大的读出余量并且具有小的电路面积。 来自单个偏置电路的电压输出被施加到存储元件的栅极和用作参考电流源的NMOS晶体管的栅极，以与流过存储元件的电流进行比较。 因此，栅极由相同的电压控制，因此工作温度范围和工作电源电压范围的特性波动减小。 因此，可以获得用于区分数据0和1的大的读出余量，导致简化的电路配置。

公开(公告)号：US20130182817A1

公开(公告)日：2013-07-18

申请号：US13738476

申请日：2013-01-10

Applicant: Seiko Instruments Inc.

Inventor： Yasushi IMAI

IPC: H03K23/00

CPC classification number: H03K23/00 ,  H03K23/42

Abstract: The timing generation circuit includes a binary counter constituted of three T-flip-flop circuits, and a binary state at reset of the binary counter is also used at system reset and in generation of the output pulses, to generate eight output pulses having different timings from eight binary states generated by the binary counter and including the state at the reset. At the system reset, a reset signal to the binary counter is delayed, so that an output of a decoder circuit at the reset of the binary counter is delayed. Therefore, the output of the decoder circuit is masked with a fast reset signal, so that the output of the decoder circuit at the system reset can be prevented from being reflected in an output terminal.

Abstract translation: 定时生成电路包括由三个T触发器电路构成的二进制计数器，并且二进制计数器的复位时的二进制状态也用于系统复位和产生输出脉冲，以产生具有不同定时的八个输出脉冲 由二进制计数器产生的8个二进制状态，并包括复位状态。 在系统复位时，二进制计数器的复位信号被延迟，使得在二进制计数器的复位时解码器电路的输出被延迟。 因此，解码器电路的输出被快速复位信号屏蔽，从而可以防止在系统复位时解码器电路的输出反映在输出端子中。