公开(公告)号：US20070285990A1

公开(公告)日：2007-12-13

申请号：US11648293

申请日：2006-12-29

Applicant: Seung-Won Lee

Inventor： Seung-Won Lee

IPC: G11C11/34

CPC classification number: G11C16/26 ,  G11C7/12 ,  G11C7/14 ,  G11C16/24

Abstract: Provided are a semiconductor device and a method for compensating for a voltage drop of a bit line. The semiconductor device includes at least one monitoring bit line and at least one main memory bit line, and monitors a voltage of the at least one monitoring bit line after a precharging operation and supplies a predetermined compensation current to the at least one monitoring bit line and the at least one main memory bit line based on a monitoring result. Accordingly, it is possible to precisely compensate for a voltage drop occurring in the main memory bit line due to under precharge or leakage current, thereby preventing unnecessary compensation current from being supplied. Therefore, it is possible to stably perform a read operation of the semiconductor device.

Abstract translation: 提供一种用于补偿位线的电压降的半导体器件和方法。 所述半导体器件包括至少一个监视位线和至少一个主存储器位线，并且在预充电操作之后监视所述至少一个监视位线的电压，并将预定补偿电流提供给所述至少一个监视位线;以及 所述至少一个主存储器位线基于监视结果。 因此，可以精确地补偿由于在预充电或漏电流之下在主存储器位线中发生的电压降，从而防止不必要的补偿电流被提供。 因此，可以稳定地执行半导体器件的读取操作。

公开(公告)号：US07098018B2

公开(公告)日：2006-08-29

申请号：US10481531

申请日：2002-07-06

Applicant: Young-Phil Lee ,  Seung-won Lee ,  Chul-ho Jung ,  Hyung-Cheol Kim ,  Soon-Yong Choi ,  Jin-suk Kim ,  Hyun-Sik Kim ,  Jung-Woo Seo

Inventor： Young-Phil Lee ,  Seung-won Lee ,  Chul-ho Jung ,  Hyung-Cheol Kim ,  Soon-Yong Choi ,  Jin-suk Kim ,  Hyun-Sik Kim ,  Jung-Woo Seo

IPC: C12N9/56 ,  C12N15/57 ,  C12N15/74 ,  C12P21/06

CPC classification number: C12N9/54

Abstract: The present invention relates to novel aminopeptidase derived from Bacillus licheniformis, a gene encoding the aminopeptidase, an expression vector containing the gene, a cell transformant transfected with the expression vector and a process for preparing a natural type protein using thereof. More particularly, the present invention relates to a gene encoding aminopeptidase which is cloned and manufactured using the recombinant DNA technique, an expression vector containing the gene, a cell transformant transfected with the expression vector and a recombinant aminopeptidase which is necessary to produce recombinant human growth hormone in a natural type protein and can be expressed in a high yield more stably and advantageously, compared with conventional methods for the purification.

Abstract translation: 本发明涉及来源于地衣芽孢杆菌的新氨基肽酶，编码氨基肽酶的基因，含有该基因的表达载体，用表达载体转染的细胞转化体和使用其制备天然型蛋白质的方法。 更具体地，本发明涉及使用重组DNA技术克隆和制造的氨基肽酶的基因，含有该基因的表达载体，用表达载体转染的细胞转化体和产生重组人生长所必需的重组氨基肽酶 与常规的纯化方法相比，可以更稳定和有利地以高产率表达天然型蛋白质中的激素。

公开(公告)号：US20060139073A1

公开(公告)日：2006-06-29

申请号：US11247938

申请日：2005-10-11

Applicant: Seung-won Lee ,  Hwi-taek Chung ,  Byeong-hoon Lee

Inventor： Seung-won Lee ,  Hwi-taek Chung ,  Byeong-hoon Lee

IPC: H03L7/06

CPC classification number: H03L7/0995 ,  H03L7/0891 ,  H03L7/099 ,  H03L7/10 ,  H03L7/18 ,  H03L2207/06

Abstract: A phase locked loop (PLL) integrated circuit includes a voltage-controlled oscillator (VCO) configured to generate a clock signal at an output terminal thereof. The VCO is further configured to improve the frequency response of the PLL by varying a capacitance of the output terminal concurrently with changing a frequency of the clock signal. The VCO may include a control signal generator, which is configured to generate a plurality of control signals in response to UP and DOWN pumping signals, and an oscillator, which is configured to generate the clock signal in response to the plurality of control signals. The oscillator may be a ring oscillator, which is responsive to the plurality of control signals.

Abstract translation: 锁相环（PLL）集成电路包括被配置为在其输出端产生时钟信号的压控振荡器（VCO）。 VCO还被配置为通过改变输出端的电容同时改变时钟信号的频率来改善PLL的频率响应。 VCO可以包括控制信号发生器，其被配置为响应于UP和DOWN泵浦信号而产生多个控制信号，以及振荡器，其被配置为响应于多个控制信号而产生时钟信号。 振荡器可以是响应于多个控制信号的环形振荡器。

公开(公告)号：US07016232B2

公开(公告)日：2006-03-21

申请号：US10922122

申请日：2004-08-18

Applicant: Seung-Won Lee ,  Seung-Keun Lee

Inventor： Seung-Won Lee ,  Seung-Keun Lee

IPC: G12C16/00

CPC classification number: G11C7/062 ,  G11C7/18 ,  G11C16/04 ,  G11C16/28 ,  G11C29/24 ,  G11C29/50004

Abstract: A memory device in accordance with embodiments of the present invention includes a reference cell array and a plurality of banks. Each of the banks includes memory cells. A plurality of current copier circuits corresponds to the banks, respectively. Each of the current copier circuits copies a reference current flowing through a reference cell array to generate a reference voltage. A plurality of sense blocks correspond to the banks, respectively. Each of the sense blocks includes a plurality of sense amplifiers for sensing data from a corresponding bank in response to the reference voltage from the corresponding current copier circuit. Memory cell lay-out area is reduced, and sense speed is increased.

Abstract translation: 根据本发明的实施例的存储器件包括参考单元阵列和多个存储体。 每个银行都包含存储单元。 多个当前复印机电路分别对应于存储体。 每个当前复印机电路复制流过参考单元阵列的参考电流以产生参考电压。 多个感测块分别对应于存储体。 每个感测块包括多个读出放大器，用于响应于来自相应的当前复印机电路的参考电压来感测来自相应存储体的数据。 存储单元布局区域减少，感测速度提高。