公开(公告)号：US07298190B2

公开(公告)日：2007-11-20

申请号：US11247938

申请日：2005-10-11

Applicant: Seung-won Lee ,  Hwi-taek Chung ,  Byeong-hoon Lee

Inventor： Seung-won Lee ,  Hwi-taek Chung ,  Byeong-hoon Lee

IPC: H03L7/06

CPC classification number: H03L7/0995 ,  H03L7/0891 ,  H03L7/099 ,  H03L7/10 ,  H03L7/18 ,  H03L2207/06

Abstract: A phase locked loop (PLL) integrated circuit includes a voltage-controlled oscillator (VCO) configured to generate a clock signal at an output terminal thereof. The VCO is further configured to improve the frequency response of the PLL by varying a capacitance of the output terminal concurrently with changing a frequency of the clock signal. The VCO may include a control signal generator, which is configured to generate a plurality of control signals in response to UP and DOWN pumping signals, and an oscillator, which is configured to generate the clock signal in response to the plurality of control signals. The oscillator may be a ring oscillator, which is responsive to the plurality of control signals.

Abstract translation: 锁相环（PLL）集成电路包括被配置为在其输出端产生时钟信号的压控振荡器（VCO）。 VCO还被配置为通过改变输出端的电容同时改变时钟信号的频率来改善PLL的频率响应。 VCO可以包括控制信号发生器，其被配置为响应于UP和DOWN泵浦信号而产生多个控制信号，以及振荡器，其被配置为响应于多个控制信号而产生时钟信号。 振荡器可以是响应于多个控制信号的环形振荡器。

公开(公告)号：US20060139073A1

公开(公告)日：2006-06-29

申请号：US11247938

申请日：2005-10-11

Applicant: Seung-won Lee ,  Hwi-taek Chung ,  Byeong-hoon Lee

Inventor： Seung-won Lee ,  Hwi-taek Chung ,  Byeong-hoon Lee

IPC: H03L7/06

CPC classification number: H03L7/0995 ,  H03L7/0891 ,  H03L7/099 ,  H03L7/10 ,  H03L7/18 ,  H03L2207/06

Abstract: A phase locked loop (PLL) integrated circuit includes a voltage-controlled oscillator (VCO) configured to generate a clock signal at an output terminal thereof. The VCO is further configured to improve the frequency response of the PLL by varying a capacitance of the output terminal concurrently with changing a frequency of the clock signal. The VCO may include a control signal generator, which is configured to generate a plurality of control signals in response to UP and DOWN pumping signals, and an oscillator, which is configured to generate the clock signal in response to the plurality of control signals. The oscillator may be a ring oscillator, which is responsive to the plurality of control signals.

Abstract translation: 锁相环（PLL）集成电路包括被配置为在其输出端产生时钟信号的压控振荡器（VCO）。 VCO还被配置为通过改变输出端的电容同时改变时钟信号的频率来改善PLL的频率响应。 VCO可以包括控制信号发生器，其被配置为响应于UP和DOWN泵浦信号而产生多个控制信号，以及振荡器，其被配置为响应于多个控制信号而产生时钟信号。 振荡器可以是响应于多个控制信号的环形振荡器。

公开(公告)号：US20060114072A1

公开(公告)日：2006-06-01

申请号：US11289286

申请日：2005-11-30

Applicant: Seung-won Lee ,  Hwi-taek Chung ,  Byeong-hoon Lee

Inventor： Seung-won Lee ,  Hwi-taek Chung ,  Byeong-hoon Lee

IPC: H03K3/03

CPC classification number: H03L7/0995 ,  H03K3/00 ,  H03K3/0315 ,  H03K17/00 ,  H03L7/0802 ,  H03L7/18

Abstract: Methods and apparatuses for changing capacitance are provided. The apparatus may adjust a current supplied to a load capacitor according to the frequency of an input clock signal. When operating at a lower frequency, a capacitance may be increased such that noise immunity may be increased. When operating at a higher frequency, a capacitance may be decreased such that current consumption may be reduced.

Abstract translation: 提供了改变电容的方法和装置。 该装置可以根据输入时钟信号的频率调节提供给负载电容器的电流。 当以较低的频率操作时，可以增加电容，使得可以增加抗噪声性。 当以更高的频率工作时，可以减小电容，从而可以降低电流消耗。

公开(公告)号：US07035162B2

公开(公告)日：2006-04-25

申请号：US10873104

申请日：2004-06-21

Applicant: Hwi-taek Chung ,  Byeong-hoon Lee

Inventor： Hwi-taek Chung ,  Byeong-hoon Lee

IPC: G11C8/00

CPC classification number: G11C16/08 ,  G11C8/08 ,  G11C8/10 ,  G11C8/12 ,  G11C8/14

Abstract: A memory device includes a predecoder that receives a row address and responsively generates a plurality of memory block selection signals, a plurality of word line selection signals, a plurality of source line selection signals, and a plurality of sub-block selection signals including respective groups of signals that correspond to respective levels of a hierarchy of sub-blocks in a plurality of memory blocks. The device further includes a global decoder that receives the sub-block selection signals and responsively generates segment activation signals for respective segments of memory blocks that correspond to respective sub-blocks at a lowest level of the hierarchy of sub-blocks. A plurality of word line decoders are coupled to word lines of respective ones of plurality of the memory blocks, with each word line decoder configured to receive the segment activation signals, a memory block selection signal and the word line selection signals and to responsively generate word line signals on the word lines coupled thereto. A plurality of source line decoders are coupled to source lines of respective ones of the plurality of memory blocks, each source line decoder configured to receive the segment activation signals, with a memory block selection signal, and the source line selection signals and to responsively generate source line signals one the source lines coupled thereto.

Abstract translation: 一种存储装置，包括接收行地址并响应地产生多个存储块选择信号的预解码器，多个字线选择信号，多个源极线选择信号和包括各组的多个子块选择信号 的信号，其对应于多个存储块中的子块的层级的各个级别。 该设备还包括全局解码器，其接收子块选择信号，并且响应于生成对应于子块层级的最低级别处的相应子块的存储器块的各个段的段激活信号。 多个字线解码器被耦合到多个存储块中的各个字线的字线，每个字线解码器被配置为接收段激活信号，存储块选择信号和字线选择信号，并响应地产生字 在与其耦合的字线上的线信号。 多个源极线解码器被耦合到多个存储器块中的相应源的源极线，每个源极线解码器被配置为利用存储器块选择信号和源极线选择信号接收段激活信号，并且响应地产生 源极线将与其耦合的源极线信号一个。

公开(公告)号：US20050007859A1

公开(公告)日：2005-01-13

申请号：US10873104

申请日：2004-06-21

Applicant: Hwi-taek Chung ,  Byeong-hoon Lee

Inventor： Hwi-taek Chung ,  Byeong-hoon Lee

IPC: G11C8/08 ,  G11C8/10 ,  G11C8/12 ,  G11C8/14 ,  G11C16/08 ,  G11C7/00

CPC classification number: G11C16/08 ,  G11C8/08 ,  G11C8/10 ,  G11C8/12 ,  G11C8/14

Abstract: A memory device includes a predecoder that receives a row address and responsively generates a plurality of memory block selection signals, a plurality of word line selection signals, a plurality of source line selection signals, and a plurality of sub-block selection signals including respective groups of signals that correspond to respective levels of a hierarchy of sub-blocks in a plurality of memory blocks. The device further includes a global decoder that receives the sub-block selection signals and responsively generates segment activation signals for respective segments of memory blocks that correspond to respective sub-blocks at a lowest level of the hierarchy of sub-blocks. A plurality of word line decoders are coupled to word lines of respective ones of plurality of the memory blocks, with each word line decoder configured to receive the segment activation signals, a memory block selection signal and the word line selection signals and to responsively generate word line signals on the word lines coupled thereto. A plurality of source line decoders are coupled to source lines of respective ones of the plurality of memory blocks, each source line decoder configured to receive the segment activation signals, with a memory block selection signal, and the source line selection signals and to responsively generate source line signals one the source lines coupled thereto.

Abstract translation: 一种存储装置，包括接收行地址并响应地产生多个存储块选择信号的预解码器，多个字线选择信号，多个源极线选择信号和包括各组的多个子块选择信号 的信号，其对应于多个存储块中的子块的层级的各个级别。 该设备还包括全局解码器，其接收子块选择信号，并且响应于生成对应于子块层级的最低级别处的相应子块的存储器块的各个段的段激活信号。 多个字线解码器被耦合到多个存储块中的各个字线的字线，每个字线解码器被配置为接收段激活信号，存储块选择信号和字线选择信号，并响应地产生字 在与其耦合的字线上的线信号。 多个源极线解码器被耦合到多个存储器块中的相应源的源极线，每个源极线解码器被配置为利用存储器块选择信号和源极线选择信号接收段激活信号，并且响应地产生 源极线将与其耦合的源极线信号一个。