公开(公告)号：US06383904B1

公开(公告)日：2002-05-07

申请号：US09690081

申请日：2000-10-16

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L213205

CPC classification number: H01L29/6675 ,  H01L29/4908 ,  H01L29/78639 ,  H01L29/78648

Abstract: For fabricating a field effect transistor on a semiconductor substrate in SOI (semiconductor on insulator) technology, a first layer of dielectric material is formed on the semiconductor substrate, and a layer of amorphous semiconductor material is deposited on the first layer of dielectric material. A second layer of dielectric material is deposited on the layer of amorphous semiconductor material, and a front gate opening is etched through the second layer of dielectric material to expose the layer of amorphous semiconductor material through the front gate opening. An amorphization dopant is implanted into the semiconductor substrate through the front gate opening to form a back gate region of amorphous semiconductor material in the semiconductor substrate such that the back gate region is formed to be aligned under the front gate opening. In addition, a back gate dopant is implanted into the back gate region of amorphous semiconductor material through the front gate opening. A gate dielectric is formed at the bottom of the front gate opening to contact the layer of amorphous semiconductor material, and a remaining portion of the front gate opening is filled with a gate electrode material. In this manner, because the same front gate opening is used for forming both the front gate electrode and the back gate region, the front gate electrode and the back gate region are substantially aligned with each other to ensure that the back gate region overlaps the front gate electrode. Thus, the area of the back gate region is minimized to be substantially aligned to the area of the channel region under the gate dielectric. A minimized area of the back gate region in turn minimizes the parasitic capacitance from the back gate region to enhance the speed performance of the MOSFET.

Abstract translation: 为了在SOI（绝缘体上半导体）技术的半导体衬底上制造场效应晶体管，在半导体衬底上形成第一层电介质材料，并且在第一绝缘材料层上沉积非晶半导体材料层。 第二层电介质材料沉积在非晶半导体材料层上，并且通过第二介电材料层蚀刻前栅极开口以通过前栅极开口暴露非晶半导体材料层。 非晶化掺杂剂通过前栅极开口注入到半导体衬底中，以在半导体衬底中形成非晶半导体材料的背栅极区域，使得背栅区域形成为在前栅极开口下对准。 此外，背栅掺杂剂通过前栅极开口注入到非晶半导体材料的背栅区域中。 栅极电介质形成在前栅极开口的底部以与非晶半导体材料层接触，并且前栅极开口的剩余部分填充有栅电极材料。 以这种方式，由于使用相同的前栅极开口来形成前栅极电极和后栅极区域，所以前栅电极和后栅极区域基本上彼此对准，以确保后栅极区域与前栅极区域重叠 栅电极。 因此，背栅极区域的面积被最小化以与栅极电介质下方的沟道区域的区域基本对齐。 背栅极区域的最小化面积进而将来自背栅极区域的寄生电容最小化，以增强MOSFET的速度性能。

公开(公告)号：US06380019B1

公开(公告)日：2002-04-30

申请号：US09187498

申请日：1998-11-06

Applicant: Bin Yu ,  Ming-Ren Lin ,  Shekhar Pramanick

Inventor： Bin Yu ,  Ming-Ren Lin ,  Shekhar Pramanick

IPC: H01L2976

CPC classification number: H01L21/74 ,  H01L29/0649 ,  H01L29/6659

Abstract: A thin filmed fully-depleted silicon-on-insulator (SOI) metal oxide semiconductor field effect transistor (MOSFET) utilizes a local insulation structure. The local insulative structure includes a buried silicon dioxide region under the channel region. The MOSFET body thickness is very small and yet silicon available outside of the channel region and buried silicon dioxide region is available for sufficient depths of silicide in the source and drain regions. The buried silicon dioxide region can be formed by a trench isolation technique or a LOCOS technique.

Abstract translation: 薄膜完全耗尽的绝缘体上硅（SOI）金属氧化物半导体场效应晶体管（MOSFET）利用局部绝缘结构。 局部绝缘结构包括沟道区下方的埋置二氧化硅区域。 MOSFET体的厚度非常小，而在沟道区域和掩埋的二氧化硅区域之外可用的硅可用于源极和漏极区域中足够的硅化物深度。 掩埋的二氧化硅区域可以通过沟槽隔离技术或LOCOS技术形成。

公开(公告)号：US06356213B1

公开(公告)日：2002-03-12

申请号：US09583601

申请日：2000-05-31

Applicant: Dawei Huang ,  Bin Yu

Inventor： Dawei Huang ,  Bin Yu

IPC: H03M700

CPC classification number: G06T9/004 ,  H03M7/30

Abstract: A lossless encoding methodology is described based on residual coding techniques and using a modified Least Mean Squares methodology to develop a predictor for a signal to be encoded, and a residual as the difference between the signal and its predicted value. After the residual for an input signal segment is obtained according to the method of the invention, that method is again applied to the residual value process to develop a second predictor, from which a second residual value is obtained. The method is then applied for at least one further iteration to the most recently obtained residual value process to develop a third predictor for the signal to be encoded. A single prediction value is then selected as a statistical representative of those multiple predictor values. The residual value to be used for encoding the input signal increment is determined as the difference between the signal value and the selected predictor value.

Abstract translation: 基于残差编码技术描述无损编码方法，并使用经修改的最小均方法来修正要编码的信号的预测器，以及残差作为信号与其预测值之间的差值。 在根据本发明的方法获得输入信号段的残差之后，再次将该方法应用于剩余值过程以开发第二预测器，从其获得第二残差值。 然后将该方法应用于最近获得的残余值过程的至少一个进一步迭代，以开发待编码信号的第三预测器。 然后选择单个预测值作为那些多个预测值的统计代表。 将用于编码输入信号增量的剩余值确定为信号值和所选择的预测值之间的差值。

公开(公告)号：US06342410B1

公开(公告)日：2002-01-29

申请号：US09612781

申请日：2000-07-10

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L2184

CPC classification number: H01L29/785 ,  H01L27/1203 ,  H01L29/42384 ,  H01L29/66795

Abstract: For fabricating a field effect transistor, a semiconductor pillar is formed on a layer of insulating material with a top surface and first and second side surfaces of the semiconductor pillar being exposed. A layer of dielectric material is formed on the top surface and the first and second side surfaces of the semiconductor pillar. A layer of conductive material is deposited on the layer of dielectric material on the top surface and the first and second side surfaces of the semiconductor pillar. A dummy dielectric structure is formed that covers a portion of the layer of conductive material such that a remaining portion of the layer of conductive material on the semiconductor pillar is exposed. The dummy dielectric structure has a predetermined sidewall on the layer of conductive material on the semiconductor pillar. A layer of hardmask dielectric is deposited on top and on the predetermined sidewall of the dummy dielectric structure and on the remaining portion of the layer of conductive material that is exposed. The layer of hardmask dielectric is anisotropically etched such that the hardmask dielectric remains at the predetermined sidewall of the dummy dielectric structure to form a spacer of hardmask dielectric. Any exposed region of the layer of conductive material and the layer of dielectric material not covered by the spacer of hardmask dielectric is etched away. The conductive material and the dielectric material that remain on the top surface and the first and second side surfaces at the gate portion of the semiconductor pillar form a three-sided gate structure and a three-sided gate dielectric of the field effect transistor for minimizing short channel effects in the field effect transistor.

Abstract translation: 为了制造场效应晶体管，半导体柱形成在绝缘材料层上，半导体柱的上表面和第一和第二侧表面露出。 在半导体柱的顶表面和第一和第二侧表面上形成介电材料层。 一层导电材料沉积在半导体柱的顶表面和第一和第二侧表面上的电介质材料层上。 形成覆盖导电材料层的一部分的虚拟介电结构，使得半导体柱上的导电材料层的剩余部分露出。 虚设电介质结构在半导体柱上的导电材料层上具有预定的侧壁。 一层硬掩模电介质沉积在虚拟电介质结构的顶部和预定侧壁上以及暴露的导电材料层的剩余部分上。 硬掩模电介质层被各向异性地蚀刻，使得硬掩模电介质保留在虚拟电介质结构的预定侧壁处以形成硬掩模电介质的间隔物。 导电材料层的任何暴露区域和未被硬掩模电介质间隔物覆盖的电介质材料层被蚀刻掉。 保留在顶表面上的导电材料和电介质材料以及在半导体柱的栅极部分处的第一和第二侧表面形成用于最小化短路的场效应晶体管的三面栅极结构和三面栅极电介质 通道效应在场效应晶体管中。

公开(公告)号：US06333244B1

公开(公告)日：2001-12-25

申请号：US09491422

申请日：2000-01-26

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L2972

CPC classification number: H01L21/8238

Abstract: A method of fabricating an integrated circuit with ultra-shallow source/drain junctions utilizes a dual amorphization technique. The technique creates a shallow amorphous region and a deep amorphous region. The shallow amorphous region is between 10-15 nm below the top surface of the substrate, and the deep amorphous region is between 150-200 nm below the top surface of the substrate. The process can be utilized for P-channel or N-channel metal oxide semiconductor field effect transistors (MOSFETs). In the case of a P-channel MOSFET, a nitrogen barrier is formed in the P-channel gate prior to p+ doping. Annealing the gate conductor is done in a step separate from the source/drain region annealing step.

Abstract translation: 制造具有超浅源极/漏极结的集成电路的方法采用双非晶化技术。 该技术产生浅的非晶区和深非晶区。 浅非晶区域在衬底的顶表面之下10-15nm之间，深非晶区域在衬底顶表面之下的150-200nm之间。 该过程可用于P沟道或N沟道金属氧化物半导体场效应晶体管（MOSFET）。 在P沟道MOSFET的情况下，在P +掺杂之前，在P沟道栅极中形成氮势垒。 在与源极/漏极区域退火步骤分离的步骤中进行栅极导体的退火。

公开(公告)号：US06320228B1

公开(公告)日：2001-11-20

申请号：US09483678

申请日：2000-01-14

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L2701

CPC classification number: H01L27/1203

Abstract: An integrated circuit includes multiple active layers. Preferably, a semiconductor-on-insulator (SOI) or silicon-on-insulator wafer is utilized to house a first active layer. A second active layer is provided by bonding a bulk substrate to the SOI substrate and removing the bulk substrate to leave a thin semiconductor layer. Subsequent active layers can be added by a similar technique. Preferably, the bulk substrates utilize a hydrogen implant to provide a breaking interface.

Abstract translation: 集成电路包括多个有源层。 优选地，使用绝缘体上半导体（SOI）或绝缘体上硅晶片来容纳第一有源层。 通过将体基板结合到SOI衬底并去除体基板以留下薄的半导体层来提供第二有源层。 后续活动层可以通过类似的技术添加。 优选地，本体衬底利用氢注入来提供断开界面。

公开(公告)号：US06319798B1

公开(公告)日：2001-11-20

申请号：US09405266

申请日：1999-09-23

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L21425

CPC classification number: H01L29/6659 ,  H01L21/26506 ,  H01L21/2658 ,  H01L21/26586 ,  H01L29/1083 ,  H01L29/6653 ,  H01L29/7833

Abstract: A method for reducing lateral dopant gradient diffusion in the source/drain extension (SDE) region of a MOSFET includes forming the deep source and drain using high temperature dopant activation annealing, and then implanting a preamorphization species in an amorphized extension region that is to become the SDE region. Then, both SDE dopant and, if desired, halo dopant are implanted into the amorphized extension region and activated using relatively low temperature annealing, thereby reducing the thermal budget of the process and concomitantly reducing unwanted dopant thermal diffusion.

Abstract translation: 用于减小MOSFET的源极/漏极延伸（SDE）区域中的横向掺杂剂梯度扩散的方法包括使用高温掺杂剂激活退火形成深源极和漏极，然后在将要成为的非晶化延伸区域中植入预变质物质 SDE地区。 然后，将SDE掺杂剂和如果需要的话，卤素掺杂剂注入到非晶化延伸区域中，并使用相对低温退火进行活化，由此降低了该工艺的热预算并伴随地减少了不需要的掺杂剂热扩散。

公开(公告)号：US06312998B1

公开(公告)日：2001-11-06

申请号：US09690073

申请日：2000-10-16

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L21336

CPC classification number: H01L29/6653 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659

Abstract: For fabricating a field effect transistor, a gate structure is formed on a gate dielectric on an active device area of a semiconductor substrate. A liner layer of a non-dielectric material is formed on sidewalls of the gate dielectric, and on a drain extension area and a source extension area of the active device area of the semiconductor substrate. First spacers of dielectric material are formed on the liner layer at sidewalls of the gate structure and over the drain and source extension areas. A contact junction dopant is implanted into exposed regions of the active device area of the semiconductor substrate to form a drain contact junction and a source contact junction. The first spacers of dielectric material are etched using a first type of etching reactant that etches the first spacers but not the liner layer such that the gate dielectric is not exposed to the first type of etching reactant. The liner layer of the non-dielectric material is etched using a second type of etching reactant that etches the liner layer but not the gate structure and the gate dielectric. A first thermal anneal is performed to activate the contact junction dopant within the drain and source contact junctions. After this first thermal anneal, a drain extension junction is formed in the drain extension area and a source extension junction is formed in the source extension area by implantation of an extension junction dopant. In this manner, the drain and source extension junctions are not heated up during the first thermal anneal for activating the contact junction dopant. Thus, transient enhanced diffusion of the extension junction dopant is minimized to maintain the shallow depth of the drain and source extension junctions such that short-channel effects are minimized for the field effect transistor having scaled down dimensions.

Abstract translation: 为了制造场效应晶体管，在半导体衬底的有源器件区域上的栅极电介质上形成栅极结构。 在栅极电介质的侧壁上以及在半导体衬底的有源器件区域的漏极延伸区域和源极延伸区域上形成非电介质材料的衬里层。 介电材料的第一间隔物在栅极结构的侧壁和漏极和源极延伸区域的衬里层上形成。 将接触结掺杂剂注入到半导体衬底的有源器件区域的暴露区域中以形成漏极接触结和源极接触结。 使用蚀刻第一间隔物而不是衬里层的第一类型蚀刻反应物蚀刻介电材料的第一间隔物，使得栅极电介质不暴露于第一类型的蚀刻反应物。 使用蚀刻衬里层而不是栅极结构和栅极电介质的第二类型蚀刻反应物来蚀刻非介电材料的衬里层。 执行第一热退火以激活漏极和源极接触接合处的接触结掺杂剂。 在该第一热退火之后，在漏极延伸区域中形成漏极延伸结，并且通过注入延伸结掺杂剂在源极延伸区域中形成源极延伸结。 以这种方式，在用于激活接触结掺杂剂的第一热退火期间，漏极和源极延伸接头不被加热。 因此，延伸结掺杂剂的瞬时增强的扩散被最小化以保持漏极和源极延伸结的浅深度，使得对具有缩小尺寸的场效应晶体管的短沟道效应最小化。

公开(公告)号：US06291302B1

公开(公告)日：2001-09-18

申请号：US09483528

申请日：2000-01-14

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L21336

CPC classification number: H01L21/268 ,  H01L21/26513 ,  H01L21/324 ,  H01L29/6659

Abstract: A method of providing a field effect transistor includes depositing a layer of a laser-reflective material on a substrate which has an active region and an inactive region; selectively removing portions of the deposited layer disposed over the active region; exposing laser energy to activate dopants in the active region; and stripping the deposited layer.

Abstract translation: 提供场效应晶体管的方法包括在具有有源区和非活性区的衬底上沉积激光反射材料层; 选择性地去除设置在有源区上的沉积层的部分; 暴露激光能量以激活有源区中的掺杂剂; 并剥离沉积层。

公开(公告)号：US06284630B1

公开(公告)日：2001-09-04

申请号：US09421304

申请日：1999-10-20

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L2104

CPC classification number: H01L29/6659 ,  H01L21/26506 ,  H01L21/2652 ,  H01L21/26586 ,  H01L21/268 ,  H01L29/665

Abstract: Drain and source extensions that are abrupt and shallow and that have high concentration of dopant are fabricated for a field effect transistor, using a laser thermal process. A drain amorphous region is formed by implanting a neutral species into a drain region of the field effect transistor at an angle directed toward a gate of the field effect transistor such that the drain amorphous region is a trapezoidal shape that extends to be sufficiently under the gate of the field effect transistor. A source amorphous region is formed by implanting the neutral species into a source region of the field effect transistor at an angle directed toward the gate of the field effect transistor such that the source amorphous region is a trapezoidal shape that extends to be sufficiently under the gate of the field effect transistor. A drain and source dopant is implanted into the drain and source amorphous regions at an angle directed toward the gate of the field effect transistor. A laser beam is then applied to the drain and source amorphous regions such that the drain and source dopant is activated within the drain and source amorphous regions in a laser thermal process. The drain and source extensions are formed by the activation of the drain and source dopant in the drain and source amorphous regions respectively during the laser thermal process. The trapezoidal shape of the drain and source extensions minimizes the series resistance and the leakage current in the field effect transistor having scaled down dimensions.

Abstract translation: 使用激光热处理为场效应晶体管制造突变和浅的并且具有高浓度掺杂剂的漏极和源极延伸。 通过以场效应晶体管的栅极朝向场效应晶体管的栅极注入中性物质到场效应晶体管的漏极区域中形成漏极非晶区域，使得漏极非晶区域是梯形形状，其延伸到栅极下方 的场效应晶体管。 源极非晶区域是通过将中性物质注入场效应晶体管的源极区域而形成的，其角度指向场效应晶体管的栅极，使得源极非晶区域是梯形形状，其延伸足以在栅极 的场效应晶体管。 漏极和源极掺杂剂以指向场效应晶体管的栅极的角度注入到漏极和源极非晶区域中。 然后将激光束施加到漏极和源极非晶区域，使得漏极和源极掺杂剂在激光热处理中在漏极和源非晶区域内被激活。 漏极和源极延伸部分分别在激光热处理期间激活漏极和源非晶区域中的漏极和源极掺杂物。 漏极和源极延伸的梯形形状使具有缩小尺寸的场效应晶体管中的串联电阻和漏电流最小化。