-
公开(公告)号：US20220084596A1
公开(公告)日：2022-03-17
申请号：US17022908
申请日：2020-09-16
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Michael Sheperek , Bruce A. Liikanen , Steve Kientz
Abstract: A first current bin boundary for a first voltage bin on a first target die of a set of dies at a memory device is identified by accessing a block family metadata table including an entry for each block family of a memory device. The first current bin boundary corresponds to a first block family associated with the first voltage bin. A first bin boundary offset between the first block family and a second block family corresponding to a first new bin boundary for the first voltage bin is determined. The first bin boundary is determined based on a calibration scan performed for the first voltage bin. A first new bin boundary for the first voltage bin is determined on each die of the set of dies based on the first bin boundary offset.
-
公开(公告)号：US20220076763A1
公开(公告)日：2022-03-10
申请号：US17530368
申请日：2021-11-18
Applicant: Micron Technology, Inc.
Inventor： Larry J. Koudele , Bruce A. Liikanen , Michael Sheperek
Abstract: An example memory sub-system includes a memory device and a processing device, operatively coupled to the memory device. The processing device is configured to identify a set of embedded servo cells stored on the memory device; determine a read voltage offset by performing read level calibration based on the set of embedded servo cells; and apply the read voltage offset for reading a memory page associated with the set of embedded servo cells.
-
公开(公告)号：US20220066639A1
公开(公告)日：2022-03-03
申请号：US17090171
申请日：2020-11-05
Applicant: Micron Technology, Inc.
Inventor： Michael Sheperek , Bruce A. Liikanen , Peter Feeley , Larry J. Koudele , Shane Nowell , Steven Michael Kientz
IPC: G06F3/06
Abstract: An example memory sub-system includes a memory device and a processing device, operatively coupled to the memory device. The processing device is configured to perform operations comprising opening a block family associated with the memory device; initialize a timer associated with the block family; assigning a plurality of cursors to the block family; responsive to programming a first block associated with a first cursor of the memory device, associating the first block with the block family; responsive to programming a second block associated with a second cursor of the memory device, associating the second block with the block family; and responsive to detecting expiration of the timer, closing the block family.
-
公开(公告)号：US11231995B2
公开(公告)日：2022-01-25
申请号：US16746786
申请日：2020-01-17
Applicant: Micron Technology, Inc.
Inventor： Mustafa N. Kaynak , Larry J. Koudele , Michael Sheperek , Patrick R. Khayat , Sampath K. Ratnam
Abstract: A first data stored at a first portion of a memory cell and a second data stored at a second portion of the memory cell are identified. A first error rate associated with first data stored at the first portion of the memory cell is determined. The first error rate is adjusted to exceed a second error rate associated with the second data stored at the second portion of the memory cell. A determination is made as to whether the first error rate exceeds a threshold. The second data stored at the second portion of the memory cell is provided for use in an error correction operation by a controller associated with the memory cell in response to determining that the first error rate exceeds the threshold.
-
公开(公告)号：US11210154B2
公开(公告)日：2021-12-28
申请号：US17100825
申请日：2020-11-21
Applicant: Micron Technology, Inc.
Inventor： Michael Sheperek , Bruce A. Liikanen , Larry J. Koudele , James P. Crowley , Stuart A. Bell
Abstract: Feedback relating to errors in memory operations on a plurality of memory cells is received by a memory sub-system. At least one processing level corresponding to a program distribution is updated based on the feedback to adjust an error measure between pages of the plurality of memory cells and to adjust a read window budget within a page of the plurality of cells. The updating of the at least one processing level is based on information for the at least one processing level that is stored in a data-structure.
-
Patent Agency Ranking
公开(公告)号：US20210382786A1
公开(公告)日：2021-12-09
申请号：US17445395
申请日：2021-08-18
Applicant: Micron Technology, Inc.
Inventor： Bruce A. Liikanen , Michael Sheperek
Abstract: The present disclosure is directed to logic based read sample offset operations in a memory sub-system. A processing device performs a first read, a second read, and a third read of data from a memory devices using a first center value corresponding to a first read level threshold, a negative offset value, and a positive offset value, respectively. The processing device performs a XOR operation on results from the first and second reads to obtain a first value and a XOR operation on results from the second and third reads to obtain a second value. The processing device performs a first count operation on the first value to determine a first difference bit count and a second count operation on the second value to determine a second difference bit count. The processing device can store or output the first difference bit count and the second difference bit count.
-
167.发明申请公开(公告)号：US20210366556A1
公开(公告)日：2021-11-25
申请号：US17395067
申请日：2021-08-05
Applicant: Micron Technology, Inc.
Inventor： Bruce A. Liikanen , Michael Sheperek , Larry J. Koudele
Abstract: A first logical page type and a second logical page type each comprising a plurality of programming distributions of a memory device are identified. A determination is made that the bit error rate (BER) for the first logical page type is less than a BER for the second logical page type. A set of rules corresponding to a determination that the BER for the first logical page type is less than the BER for the second logical page type is identified. A program targeting rule of the set of rules is determined based on a valley between an erase distribution and a programming distribution adjacent to the erase distribution having a lowest valley margin of a plurality of valley margins corresponding to the plurality of programming distributions of the memory device. Based on the program targeting rule, a program targeting operation is performed to adjust a voltage associated with one or more programming distributions of the memory device.
-
公开(公告)号：US20210193229A1
公开(公告)日：2021-06-24
申请号：US16719745
申请日：2019-12-18
Applicant: Micron Technology, Inc.
Inventor： Bruce A. Liikanen , Michael Sheperek , Larry J. Koudele
Abstract: A system includes a memory array with memory cells and a processing device coupled thereto. The processing device performs program targeting operations that include to: determine a set of difference error counts corresponding to programming distributions of the memory array; identify, based on a comparison of the set of difference error counts, valley margins corresponding to the programming distributions; select, based on values of the valley margins, a program targeting rule from a set of rules; perform, based on the program targeting rule, a program targeting operation to adjust a voltage level associated with an erase distribution of the memory array; determine a bit error rate (BER) of the memory array; in response to the BER satisfying a BER control value, reduce the voltage level by a voltage step; and in response to the BER not satisfying the BER control value, increase the voltage level by the voltage step.
-
公开(公告)号：US20210011656A1
公开(公告)日：2021-01-14
申请号：US16507844
申请日：2019-07-10
Applicant: Micron Technology, Inc.
Inventor： Michael Sheperek , Bruce A. Liikanen
Abstract: The present disclosure is directed to read sample offset most probable bit operation associated with a memory component. A processing device performs a first read, a second read, and a third read of data from the memory component using a center value corresponding to a read threshold voltage value, a negative offset value, and a positive offset value, respectively. The processing device performs a most probable bit operation on the first set of data, the second set of data, and the third set of date to generate a most probable bit sequence corresponding to the data associated with the memory component. The processing device can store or output the generated most probable bit sequence.
-
公开(公告)号：US20200168282A1
公开(公告)日：2020-05-28
申请号：US16775099
申请日：2020-01-28
Applicant: Micron Technology, Inc.
Inventor： Michael Sheperek , Larry J. Koudele , Steve Kientz
Abstract: A system comprises a memory device comprising a plurality of memory cells; and a processing device coupled to the memory device, the processing device configured to iteratively: calibrate read levels based on associated read results, wherein the read levels are tracked via optimization target data that at least initially includes at least one read level in addition to a target trim; and remove a calibrated read level from the optimization target data when the calibrated read level satisfies a calibration condition.
-
-
-
-
-
-
-
-
-
Search Results
173
records
(took 0.033 seconds)
