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公开(公告)号：US20220391143A1
公开(公告)日：2022-12-08
申请号：US17819857
申请日：2022-08-15
Applicant: Micron Technology, Inc.
Inventor： Michael Sheperek , Larry J. Koudele , Steve Kientz
Abstract: A memory device includes a processing device configured to iteratively update a center read level according to a first step size after reading a subset of memory cells according to a set of read levels including the center read level; track an update direction for the processing device to use when iteratively updating the center read level, wherein the update direction corresponds to an increase or a decrease in the center read level; detect a change condition based on updating the center read level according to the first step size; and iteratively update the center read level according to a second step size based on detection of the change condition.
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公开(公告)号：US20220036957A1
公开(公告)日：2022-02-03
申请号：US17504467
申请日：2021-10-18
Applicant: Micron Technology, Inc.
Inventor： Michael Sheperek , Larry J. Koudele , Steve Kientz
Abstract: A system comprises a memory device comprising a plurality of memory cells; and a processing device coupled to the memory device, the processing device configured to manage optimization target data that at least initially includes read levels in addition to a target trip, wherein the optimization data is managed based on iteratively calibrating the read levels and removing the calibrated levels from the optimization target data.
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公开(公告)号：US10852953B2
公开(公告)日：2020-12-01
申请号：US16170423
申请日：2018-10-25
Applicant: Micron Technology, Inc.
Inventor： Larry J. Koudele , Bruce A. Liikanen , Steve Kientz
Abstract: A dynamic temperature compensation trim for use in temperature compensating a memory operation on a memory call of a memory component. The dynamic temperature compensation trim is based on a temperature of the memory component and based on in-service data for the memory operation on the memory cell. A register for the memory operation is modified based on the dynamic temperature compensation trim.
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公开(公告)号：US11791004B2
公开(公告)日：2023-10-17
申请号：US18081004
申请日：2022-12-14
Applicant: Micron Technology, Inc.
Inventor： Michael Sheperek , Bruce A. Liikanen , Steve Kientz , Anita Ekren , Gerald Cadloni
CPC classification number: G11C16/349 , G11C7/04 , G11C16/10 , G11C16/26 , G11C16/30 , G11C16/32 , G11C16/3404 , G11C16/3459
Abstract: A method includes associating, by a processing device, a set of dies of a block family with a die family, wherein the block family is associated with a first threshold voltage offset bin for voltage offsets to be applied in a read operation; and responsive to detecting a triggering event, associating each die of the set of dies with a second threshold voltage offset bin for voltage offsets to be applied in a read operation, wherein the second threshold voltage offset bin is selected based on a representative die of the set of dies associated with the die family.
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公开(公告)号：US20220137814A1
公开(公告)日：2022-05-05
申请号：US17084540
申请日：2020-10-29
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Shane Nowell , Michael Sheperek , Larry J. Koudele , Bruce A. Liikanen , Steve Kientz
IPC: G06F3/06
Abstract: An example memory sub-system includes a memory device and a processing device, operatively coupled to the memory device. The processing device is configured to open a first block family associated with the memory device; assign a first cursor of a plurality of cursors of the memory device to the first block family; responsive to programming a first block associated with the first cursor, associate the first block with the first block family; open, while the first block family is open, a second block family associated with the memory device; assign a second cursor of the plurality of cursors of the memory device to the second block family; and responsive to programming a second block associated with the second cursor, associate the second block with the second block family.
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Patent Agency Ranking
公开(公告)号：US11177006B2
公开(公告)日：2021-11-16
申请号：US16775099
申请日：2020-01-28
Applicant: Micron Technology, Inc.
Inventor： Michael Sheperek , Larry J. Koudele , Steve Kientz
Abstract: A system comprises a memory device comprising a plurality of memory cells; and a processing device coupled to the memory device, the processing device configured to iteratively: calibrate read levels based on associated read results, wherein the read levels are tracked via optimization target data that at least initially includes at least one read level in addition to a target trim; and remove a calibrated read level from the optimization target data when the calibrated read level satisfies a calibration condition.
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公开(公告)号：US20200241801A1
公开(公告)日：2020-07-30
申请号：US16850224
申请日：2020-04-16
Applicant: Micron Technology, Inc.
Inventor： Michael Sheperek , Larry J. Koudele , Steve Kientz
Abstract: A memory device includes a processing device configured to iteratively update a center read level according to a first step size after reading a subset of memory cells according to a set of read levels including the center read level; track an update direction for the processing device to use when iteratively updating the center read level, wherein the update direction corresponds to an increase or a decrease in the center read level; detect a change condition based on updating the center read level according to the first step size; and iteratively update the center read level according to a second step size based on detection of the change condition.
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公开(公告)号：US10664194B2
公开(公告)日：2020-05-26
申请号：US15981796
申请日：2018-05-16
Applicant: Micron Technology, Inc.
Inventor： Michael Sheperek , Larry J. Koudele , Steve Kientz
Abstract: A memory device includes a processing device configured to iteratively determine a set of read results based on reading a subset of memory cells according to a set of read levels determine an update direction based on the set of read results, wherein the update direction corresponds to one of the set of read levels; determine whether a change condition is met; generate an updated read level for the set of read levels based on applying an adjustment step to one of the read levels in the set of read levels along the update direction, wherein the adjustment step is: a first step size in response to the change condition not being met, and a second step size in response to the change condition being met.
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公开(公告)号：US20190354313A1
公开(公告)日：2019-11-21
申请号：US15981796
申请日：2018-05-16
Applicant: Micron Technology, Inc.
Inventor： Michael Sheperek , Larry J. Koudele , Steve Kientz
Abstract: A memory device includes a processing device configured to iteratively determine a set of read results based on reading a subset of memory cells according to a set of read levels determine an update direction based on the set of read results, wherein the update direction corresponds to one of the set of read levels; determine whether a change condition is met; generate an updated read level for the set of read levels based on applying an adjustment step to one of the read levels in the set of read levels along the update direction, wherein the adjustment step is: a first step size in response to the change condition not being met, and a second step size in response to the change condition being met.
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公开(公告)号：US20240329867A1
公开(公告)日：2024-10-03
申请号：US18584993
申请日：2024-02-22
Applicant: Micron Technology, Inc.
Inventor： Yee Yang Tay , Lei Zhang , Steve Kientz , Edric Goh
IPC: G06F3/06
CPC classification number: G06F3/064 , G06F3/0604 , G06F3/0629 , G06F3/0679
Abstract: Methods, apparatuses and systems related to tracking charge loss are described. An apparatus may include a tracking mechanism configured to make direct measurements for tracking charge loss in first-type cells. The apparatus may be configured to designate a set of the first-type cells as proxy for modeling charge loss at second-type cells having a different storage density than the first-type cells. The apparatus may use the tracking mechanism to make measurements on the proxy set of the first-type cells and translate the measurement to account for the charge loss at the second-type cells.
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