公开(公告)号：US09182779B1

公开(公告)日：2015-11-10

申请号：US14216395

申请日：2014-03-17

Applicant: Marvell International Ltd.

Inventor： Robert Mack ,  Timothy Chen

IPC: G06F1/02 ,  H03B28/00 ,  H03L1/00 ,  G06F1/03 ,  H03L7/099

CPC classification number: G06F1/022 ,  G06F1/0328 ,  G06F1/08 ,  H03B28/00 ,  H03B2200/0088 ,  H03L1/00 ,  H03L7/0994

Abstract: A method for compensating NCO jitter by changing a step value used to increment an accumulator in the NCO to make up for inaccuracies, or jitters. In one approach, a remainder in the accumulator may be monitored and a compensated clock close to the current edge of an ideal clock may be generated. In another approach, a compensated clock close to the next edge of the ideal clock may be generated after the current edge of the ideal clock is missed. The step value may be stored in a memory, which may be a register. A jitter compensator may include a comparator for monitoring the remainder in the accumulator or a detector for detecting whether an ideal clock has been missed. The jitter compensator may also change the step value to a step value for a faster clock to compensate jitter.

Abstract translation: 一种用于通过改变用于增加NCO中的累加器的步长值来补偿NCO抖动以补偿不准确或不稳定的方法。 在一种方法中，可以监视累加器中的余数，并且可以产生接近理想时钟的当前边缘的补偿时钟。 在另一种方法中，在理想时钟的当前边缘被错过之后，可以产生靠近理想时钟的下一个边缘的补偿时钟。 步数值可以存储在可以是寄存器的存储器中。 抖动补偿器可以包括用于监视累加器中的余数的比较器或用于检测是否错过理想时钟的检测器。 抖动补偿器还可以将步长值改变为更快时钟的步进值以补偿抖动。

公开(公告)号：US20140149723A1

公开(公告)日：2014-05-29

申请号：US14060900

申请日：2013-10-23

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Sascha Junghans ,  Matthias Klein ,  Thomas Schlipf

IPC: G06F9/30

CPC classification number: G06F7/544 ,  G06F1/0328 ,  G06F1/1615 ,  G06F7/57 ,  G06F9/3838 ,  G06F12/1018 ,  G06F17/30109 ,  G06F17/30949 ,  G06F2212/401

Abstract: Creating hash values based on bit values of an input vector. An apparatus includes a first and a second hash table, a first and second hash function generator adapted to configure a respective hash function for a creation of a first and second hash value based on the bit values of the input vector. The hash values are stored in the respective hash tables. An evaluation unit includes a comparison unit to compare a respective effectiveness of the first hash function and the second hash function, and an exchanging unit responsive to the comparison unit adapted to replace the first hash function by the second hash function.

Abstract translation: 基于输入向量的位值创建哈希值。 一种装置包括第一和第二散列表，第一和第二散列函数发生器，其适于基于输入向量的位值来配置用于创建第一和第二散列值的相应散列函数。 哈希值存储在相应的散列表中。 评估单元包括比较单元，用于比较第一散列函数和第二散列函数的相应有效性，以及响应于比较单元的交换单元，适于通过第二散列函数来替换第一散列函数。

公开(公告)号：US20140122553A1

公开(公告)日：2014-05-01

申请号：US13666289

申请日：2012-11-01

Applicant: Leo G. Dehner ,  Oded Yishay

Inventor： Leo G. Dehner ,  Oded Yishay

IPC: G06F17/14

CPC classification number: G06F17/142 ,  G06F1/0328 ,  G06F17/14

Abstract: A method and apparatus may be used to generate complex exponentials for either frequency domain or time domain applications by programming input parameter values into a complex exponential vector generator (260) having a frequency generator stage (281) and a vector phase accumulator stage (282) arranged with a vector element multiplier stage (283) to generate complex exponential phase index values (α0, α1, . . . αv-1) that are processed by a complex exponential generator stage (284) to output a plurality of complex exponential values (e.g., ej2πα0, ej2πα1, . . . ej2παv-1) that may be rearranged by a permutation unit (286) for use by vector data path.

Abstract translation: 方法和装置可以用于通过将输入参数值编程到具有频率发生器级（281）和矢量相位累加器级（282）的复指数矢量生成器（260）中来为频域或时域应用产生复指数， 布置有矢量元素乘法器级（283）以产生由复指数发生器级（284）处理的复数指数相位索引值（α0，α1，...αv-1），以输出多个复指数值 例如ej2＆pgr;α0，ej2＆pgr;α1，... ej2＆pgr;αv-1），其可以由置换单元（286）重新排列以供矢量数据路径使用。

公开(公告)号：US20130235889A1

公开(公告)日：2013-09-12

申请号：US13873623

申请日：2013-04-30

Applicant: ROCKSTAR CONSORTIUM US LP

Inventor： James AWEYA ,  Michel OUELLETTE ,  Delfin Y. MONTUNO

IPC: H04L7/00

CPC classification number: H04L7/0079 ,  G06F1/0328 ,  H03L7/0805 ,  H03L7/085 ,  H03L7/089 ,  H03L2207/50 ,  H04J3/0632 ,  H04J3/0658

Abstract: Transfer of differential timing over a packet network is provided. A transmitting service interface receives a service clock and is coupled to a receiving service interface through a network backplane. A primary reference clock is provided to time the network backplane. The primary reference clock and the service clock are used to synthesize a copy of the service clock connected to the transmitting service interface. A first control word containing an error differential between the service clock and the synthesized copy of the service clock is generated and transmitted through the network backplane via a packet. The first control word, together with the primary reference clock, is used to recreate the service clock for timing the receiving service interface.

Abstract translation: 提供了通过分组网络传输差分定时。 发送业务接口接收业务时钟，并通过网络背板耦合到接收业务接口。 提供主参考时钟来对网络背板进行时间。 主参考时钟和服务时钟用于合成连接到发送服务接口的业务时钟的副本。 生成服务时钟和服务时钟的合成副本之间的误差的第一个控制字，并经由分组通过网络背板发送。 第一个控制字与主参考时钟一起用于重新创建用于定时接收服务接口的服务时钟。

公开(公告)号：US08416124B2

公开(公告)日：2013-04-09

申请号：US12833113

申请日：2010-07-09

Applicant: Michael Gerding

Inventor： Michael Gerding

IPC: G01S13/08

CPC classification number: G06F1/0328 ,  H03B19/00 ,  H03B21/02

Abstract: A frequency synthesizer for a time base generator of a level measuring device which works according to the radar principle, with at least one first output for output of a first frequency signal, with at least one second output for output of a second frequency signal, and with a reference oscillator for producing a reference frequency signal, the first frequency signal and the second frequency signal having a small difference frequency relative to one another, the first frequency signal being producible by interaction of the reference oscillator with a direct digital synthesizer. The first frequency signal and second frequency signal can be generated with especially low noise by the second frequency signal being derived from the reference oscillator without interconnection of a direct digital synthesizer and the direct digital synthesizer being operated such that only a noise spectrum is produced which is at least partially minimized.

Abstract translation: 一种用于根据雷达原理工作的电平测量装置的时基发生器的频率合成器，具有用于输出第一频率信号的至少一个第一输出，以及用于输出第二频率信号的至少一个第二输出，以及 具有用于产生参考频率信号的参考振荡器，所述第一频率信号和所述第二频率信号相对于彼此具有小的差分频率，所述第一频率信号可通过所述参考振荡器与直接数字合成器的相互作用产生。 可以通过第二频率信号从参考振荡器得到第一频率信号和第二频率信号，而无需直接数字合成器和正在操作的直接数字合成器的互连，从而仅产生噪声谱 至少部分地最小化。

公开(公告)号：US20120229171A1

公开(公告)日：2012-09-13

申请号：US13412653

申请日：2012-03-06

Applicant: Liming Xiu ,  Ming-Chieh Lin

Inventor： Liming Xiu ,  Ming-Chieh Lin

IPC: H03B21/00

CPC classification number: G06F1/025 ,  G06F1/02 ,  G06F1/022 ,  G06F1/0328

Abstract: One of the advantages of direct frequency synthesis technique (e.g., flying-adder architecture) is its capability of generating arbitrary frequency by utilizing the time-average-frequency concept. In the clock output of the direct frequency synthesizer, instead of one type of cycle, there are two types of cycles. Unlike the conventional one-type-cycle clock wherein clock energy is concentrated at its designed frequency, Time-Average-Frequency based clock spreads some of its energy into spurious tones, which could be harmful to certain applications. The spurious tones are caused by the periodic carry sequence generated from a fractional part accumulator inside the frequency synthesizer. The invention suggests a method and an apparatus to break this periodicity and convert the spurious tones into broadband noise.

Abstract translation: 直接频率合成技术（例如飞行加法器结构）的优点之一是其通过利用时间平均频率概念产生任意频率的能力。 在直接频率合成器的时钟输出中，代替一种类型的周期，有两种类型的周期。 与其中时钟能量集中在其设计频率的常规单周期时钟不同，基于时间 - 平均频率的时钟将其一些能量扩展到伪噪声，这可能对某些应用有害。 伪噪声是由频率合成器内的分数分量累加器产生的周期性进位序列引起的。 本发明提出了一种破坏这种周期性并将伪噪声转换成宽带噪声的方法和装置。

公开(公告)号：US08125255B2

公开(公告)日：2012-02-28

申请号：US12929857

申请日：2011-02-22

Applicant: Hiroki Kimura ,  Naoki Onishi ,  Shoichi Tsuchiya

Inventor： Hiroki Kimura ,  Naoki Onishi ,  Shoichi Tsuchiya

IPC: H03L7/06

CPC classification number: H03L7/08 ,  G06F1/0328

Abstract: Provided is a PLL circuit improving reliability while suppressing power consumption without degrading noise characteristics. The PLL circuit includes a PLL IC that divides an output frequency Fout from a VCO, compares phase with a reference signal, and feeds back a phase difference as a control voltage to the VCO. A control circuit is capable of finely setting both of a reference frequency Fref and an output frequency Fdds in a DDS circuit, and the DDS circuit generates folding signals of Fdds for Fref and an integral multiple frequency thereof based on the combination of the frequencies. A first AMP amplifies a signal, a variable filter selects a desired Fdds (desired) and a second AMP amplifies the signal and supplies the same to the PLL IC as a reference signal. The control circuit further supplies a division ratio N to the PLL IC.

Abstract translation: 提供一种在不降低噪声特性的同时抑制功耗的同时提高可靠性的PLL电路。 PLL电路包括将VCO的输出频率Fout分频的PLL IC，将相位与参考信号进行比较，并将相位差作为控制电压反馈到VCO。 控制电路能够精细地设定DDS电路中的参考频率Fref和输出频率Fdds，DDS电路基于频率的组合，生成Fref的Fdds和其整数倍频率的折叠信号。 第一AMP放大信号，可变滤波器选择所需的Fdd（所需），第二AMP放大信号并将其作为参考信号提供给PLL IC。 控制电路还向PLL IC提供分频比N.

公开(公告)号：US08090755B1

公开(公告)日：2012-01-03

申请号：US11807112

申请日：2007-05-25

Applicant: Gordon Old

Inventor： Gordon Old

IPC: G06F1/02 ,  G06F7/50 ,  H03B21/00

CPC classification number: G06F7/505 ,  G06F1/022 ,  G06F1/0328 ,  G06F2211/902

Abstract: A method for accumulation of information is described. The information is separated into first portions of MSBs and second portions of LSBs. The first and second portions are respectively input to a first adder and a second adder to provide first and second sums. The first and second sums are output from a first and a second storage device for feedback input respectively to the first and second adder to provide the first and second sums. A carry bit output from the second storage device is generated responsive to each wrap condition associated with the storing of the second sums in the second storage device. The carry bit is fed back to the first adder and fed forward for subsequent consolidation with the first sums respectively output from the first storage device. The first sums and the second sums are respectively accumulated as numbers represented in a redundant number system.

Abstract translation: 描述信息累积的方法。 信息被分成MSB的第一部分和LSB的第二部分。 第一和第二部分分别输入到第一加法器和第二加法器以提供第一和第二和。 第一和第二和从第一和第二存储装置输出，用于分别反馈输入到第一和第二加法器以提供第一和第二和。 响应于与在第二存储设备中存储第二和相关联的每个包装条件而产生来自第二存储设备的进位位输出。 进位位反馈到第一加法器，并且向前馈送用于随后合并的第一和从第一存储装置输出的第一和。 第一和和第二和分别作为以冗余数字系统表示的数字累积。

公开(公告)号：US20100194444A1

公开(公告)日：2010-08-05

申请号：US12363660

申请日：2009-01-30

Applicant: Jeffery Patterson

Inventor： Jeffery Patterson

IPC: H03B21/00

CPC classification number: G06F1/0328 ,  G06F2211/902

Abstract: In an embodiment, an apparatus, comprises a phase accumulator configured to provide an output comprising a truncated phase word representative of an instantaneous phase; a multiplexer configured to provide an output representative of a phase rotation, wherein the output representative of the phase rotation is randomly selected from a group of phase rotation representation outputs; an adder configured to receive the output from the phase accumulator and the output from the multiplexer, wherein the adder provides an output representative of the instantaneous phase rotated by the phase rotation; a lookup table configured to receive the output representative of the instantaneous phase and to provide an amplitude output; and a rotator configured to receive the amplitude output and substantially to cancel the phase rotation. Other embodiments do not comprise a rotator. A method is also described.

Abstract translation: 在一个实施例中，装置包括相位累加器，其被配置为提供包括代表瞬时相位的截断相位字的输出; 多路复用器，其被配置为提供表示相位旋转的输出，其中表示相位旋转的输出是从一组相位旋转表示输出中随机选择的; 一个加法器，配置成从相位累加器接收输出和多路复用器的输出，其中加法器提供表示由相位旋转旋转的瞬时相位的输出; 查找表，被配置为接收代表瞬时相位的输出并提供振幅输出; 以及被配置为接收振幅输出并且基本上抵消相位旋转的旋转器。 其他实施例不包括旋转器。 还描述了一种方法。

公开(公告)号：US07714623B2

公开(公告)日：2010-05-11

申请号：US12100011

申请日：2008-04-09

Applicant: Peter T. A. Reilly ,  Hideya Koizumi

Inventor： Peter T. A. Reilly ,  Hideya Koizumi

IPC: H03B21/00

CPC classification number: G06F1/0328

Abstract: Jitterless transition of the programmable clock waveform is generated employing a set of two coupled direct digital synthesis (DDS) circuits. The first phase accumulator in the first DDS circuit runs at least one cycle of a common reference clock for the DDS circuits ahead of the second phase accumulator in the second DDS circuit. As a phase transition through the beginning of a phase cycle is detected from the first phase accumulator, a first phase offset word and a second phase offset word for the first and second phase accumulators are calculated and loaded into the first and second DDS circuits. The programmable clock waveform is employed as a clock input for the RAM address controller. A well defined jitterless transition in frequency of the arbitrary waveform is provided which coincides with the beginning of the phase cycle of the DDS output signal from the second DDS circuit.

Abstract translation: 使用一组两个耦合的直接数字合成（DDS）电路产生可编程时钟波形的无抖动转换。 第一DDS电路中的第一相位累加器在第二DDS电路中的第二相位累加器之前的DDS电路中运行至少一个公共参考时钟的周期。 当从第一相位累加器检测到相位周期开始的相变时，计算第一和第二相位累加器的第一相位偏移字和第二相位偏移字并将其加载到第一和第二DDS电路中。 可编程时钟波形用作RAM地址控制器的时钟输入。 提供了任意波形的频率上明确定义的无抖动转换，其与来自第二DDS电路的DDS输出信号的相位周期的开始一致。