公开(公告)号：US20050218967A1

公开(公告)日：2005-10-06

申请号：US10962371

申请日：2004-10-09

Applicant: Tahir Rashid

Inventor： Tahir Rashid

IPC: G05F3/22 ,  H03K3/42

CPC classification number: G05F3/225

Abstract: A circuit for maintaining a generated reference voltage at a substantially constant level for a range of temperatures. The circuitry comprising: a first circuit arranged to generate a first voltage having a first temperature characteristic, and a second circuit arranged to generate a second voltage having a second temperature characteristic. The second voltage compensates for the first voltage to maintain the reference voltage at a substantially constant level over a first temperature range. The circuit also having a third circuit arranged to act in a second temperature range to compensate for the first voltage to maintain the reference voltage at a substantially constant level in the second temperature range.

Abstract translation: 一种用于在一定温度范围内将所产生的参考电压维持在基本恒定水平的电路。 所述电路包括：第一电路，被布置成产生具有第一温度特性的第一电压，以及布置成产生具有第二温度特性的第二电压的第二电路。 第二电压补偿第一电压，以使参考电压在第一温度范围内保持基本恒定的电平。 电路还具有布置成在第二温度范围内作用的第三电路，以补偿第一电压，以将参考电压维持在第二温度范围内基本上恒定的电平。

公开(公告)号：US06937973B1

公开(公告)日：2005-08-30

申请号：US09344847

申请日：1999-06-28

Applicant: Gajinder Singh Panesar

Inventor： Gajinder Singh Panesar

IPC: G06F17/50 ,  G06F9/44

CPC classification number: G06F17/5045 ,  G06F2217/68

Abstract: A method of operating a computer system to design an application specific processor (ASP) comprises defining a set of peripherals for the ASP which are responsive to stimuli and which communicate with a processor, generating for each peripheral an input file which defines the functional attributes of that peripheral in a high level language with an input data structure, entering the input file into the computer system and operating a modelling tool loaded on the computer system to generate from the input file a register definition file by allocating specific elements of the input data structure to predefined sectors of a register definition table, and using the register definition file to create in silicon the registers of the ASP.

Abstract translation: 一种操作计算机系统以设计应用特定处理器（ASP）的方法包括定义一组响应于刺激并且与处理器进行通信的ASP的外围设备，为每个外围设备生成定义功能属性的输入文件 具有输入数据结构的高级语言的外围设备，将输入文件输入计算机系统并操作加载在计算机系统上的建模工具，以通过分配输入数据结构的特定元素从输入文件生成寄存器定义文件 到寄存器定义表的预定义扇区，并使用寄存器定义文件在硅中创建ASP的寄存器。

公开(公告)号：US06930509B2

公开(公告)日：2005-08-16

申请号：US10675200

申请日：2003-09-29

Applicant: Saikat-Kumar Banik

Inventor： Saikat-Kumar Banik

IPC: H03K19/177 ,  H03K19/173

CPC classification number: H03K19/17744

Abstract: A programmable flip-flop is presented for outputting data. The flip-flop includes a first latch for latching a first input value in response to a rising edge of a clock signal. A second latch latches a second input value in response to a falling edge of the clock signal. A selection function controlled by the clock signal selectively supplies outputs of the first and second latches to the input of a third latch. A control circuit for the third latch accepts as inputs the clock signal and an inverted clock signal. The programmable flip-flop is configurable to operate in at least first and second modes selectable by the selection function and third latch control circuit, such that in the first mode the output of the third latch is the first and second input values multiplexed together and output at twice the clock rate. Alternatively, in the second mode one of the first and second latches is disconnected from the third latch such that the programmable flip-flop operates as a single edge-triggered register clocking out one of the first and second input values from the third latch.

公开(公告)号：US20050172193A1

公开(公告)日：2005-08-04

申请号：US11015330

申请日：2004-12-17

Applicant: Robert Warren

Inventor： Robert Warren

IPC: G01R31/3185 ,  G01R31/28

CPC classification number: G01R31/318563 ,  G01R31/318536

Abstract: An integrated circuit comprising (i) a plurality of portions, each portion including test control circuitry; and (ii) at least one test input arranged to receive test data, wherein the test data is clocked in a plurality of time slots, with test data for different ones of the plurality of portions being allocated to different time slots.

Abstract translation: 一种集成电路，包括（i）多个部分，每个部分包括测试控制电路; 和（ii）布置成接收测试数据的至少一个测试输入，其中所述测试数据在多个时隙中计时，所述多个部分中的不同部分的测试数据被分配给不同的时隙。

公开(公告)号：US06901584B2

公开(公告)日：2005-05-31

申请号：US09997230

申请日：2001-11-29

Applicant: Richard Shann

Inventor： Richard Shann

IPC: G06F9/45

CPC classification number: G06F8/447

Abstract: A method of assembling a source code module to form an object code module, said source code module including one or more assembler directives, wherein the assembler directives are used to generate relocation instructions in the object code module, the method comprising: reading a plurality of compound relocation sequence definitions stored in a memory, each compound relocation definition sequence comprising a compound relocation indicator and a first sequence of relocation instructions; reading assembler source code from said source code module, said source code generating an associated sequence of relocation instructions for executing the directive; determining if said associated sequence of relocations matches one of said stored sequence of relocation instructions; and if a match of relocation sequences is determined, inserting into said object code module a compound relocation including the compound relocation indicator of said matched compound relocation sequence definition instruction and said matched sequence.

Abstract translation: 一种组合源代码模块以形成目标代码模块的方法，所述源代码模块包括一个或多个汇编器指令，其中汇编器指令用于在目标代码模块中生成重定位指令，该方法包括：读取多个 存储在存储器中的复合重定位序列定义，每个复合重定位定义序列包括复合重定位指示符和第一序列重定位指令; 从所述源代码模块读取汇编源代码，所述源代码生成用于执行指令的相关联的重定位指令序列; 确定所述相关联的重定位序列是否匹配所述存储的重定位指令序列之一; 并且如果确定了重定位序列的匹配，则向所述目标代码模块插入包括所述匹配复合重定位序列定义指令和所述匹配序列的复合重定位指示符的复合重定位。

公开(公告)号：US06882589B2

公开(公告)日：2005-04-19

申请号：US10444933

申请日：2003-05-23

Applicant: Paul Bailey

Inventor： Paul Bailey

IPC: G06F12/02 ,  G06F12/08 ,  G11C7/00

CPC classification number: G06F12/0215 ,  G06F12/0862 ,  G06F2212/6022

Abstract: A computer system comprising a plurality of data processing elements connected through a shared communication bus to a memory so that for a given computer cycle at least one of the elements assumes control of the bus for accessing address in memory. The computer system having memory access circuitry connected between the data processing elements and memory which has first and second buffer units for storing prefetched bursts of data from the memory. The buffer circuit also having control logic for prefetching data in sequential bursts from the memory and storing the prefetched burst in the first or second buffer units and the control logic monitors the buffer units and the address to be accessed in memory to determine in which buffer the next fetched burst should be stored.

Abstract translation: 一种计算机系统，包括通过共享通信总线连接到存储器的多个数据处理元件，使得对于给定的计算机周期，所述元件中的至少一个元件采取总线控制来访问存储器中的地址。 所述计算机系统具有连接在所述数据处理单元和存储器之间的存储器访问电路，所述存储器具有第一和第二缓冲单元，用于存储来自所述存储器的预取数据脉冲串。 缓冲电路还具有用于从存储器预取序列突发中的数据并将预取脉冲串存储在第一或第二缓冲器单元中的控制逻辑，并且控制逻辑监视缓冲器单元和要在存储器中访问的地址，以确定在哪个缓冲器中 应该存储下一个提取的突发。

公开(公告)号：US06877119B2

公开(公告)日：2005-04-05

申请号：US09954637

申请日：2001-09-14

Applicant: Christophe Lauga

Inventor： Christophe Lauga

IPC: G01R31/3185 ,  G01R31/28

CPC classification number: G01R31/318536 ,  G01R31/318547 ,  G01R31/318572

Abstract: A semiconductor integrated circuit, including a test scan arrangement has a plurality of scan chains arranged in pairs. These scan chains have input terminals for receiving test patterns, and outputs provided to compression logic such as a distributed XOR tree multiple input shift register to provide an output which is a compressed signal derived from the output test patterns. In an alternative configuration, the first scan chain of each pair is connected to the second scan chain of each pair, and the input terminal of the second scan chain becomes the output terminal. Thereby creating a longer scan chain of the first and second scan chains together with one input terminal and one output terminal. The two loads allow for efficient scanning in the first mode, or debugging to determine the position of a fault in the second mode.

Abstract translation: 包括测试扫描装置的半导体集成电路具有成对布置的多个扫描链。 这些扫描链具有用于接收测试图案的输入端子，以及提供给诸如分布式异或树多输入移位寄存器之类的压缩逻辑的输出，以提供作为从输出测试图案导出的压缩信号的输出。 在替代配置中，每对的第一扫描链连接到每对的第二扫描链，并且第二扫描链的输入端变为输出端。 从而创建第一和第二扫描链的更长的扫描链以及一个输入端和一个输出端。 两个负载允许在第一模式下进行有效的扫描，或者调试以确定第二模式中故障的位置。

公开(公告)号：US20050069038A1

公开(公告)日：2005-03-31

申请号：US10165039

申请日：2002-06-06

Applicant: Victor Watson

Inventor： Victor Watson

IPC: G06T9/00 ,  H04N7/26 ,  H04N7/50 ,  H04N7/12

CPC classification number: H04N19/42 ,  H04N19/61

Abstract: A decoding apparatus for decoding digital video data, comprising: a data memory comprising registers, each register being capable of storing a data strings comprising a plurality of data sub-strings such that the data sub-strings are not individually addressable; an input for receiving compressed video information represented by a matrix of data values and loading each data value in order into a respective one of the sub-strings; and processing means for performing an inverse zigzag operation on the matrix of data values by executing a series of reordering operations on the data strings to reorder the data sub-strings comprised therein.

Abstract translation: 一种用于解码数字视频数据的解码装置，包括：数据存储器，包括寄存器，每个寄存器能够存储包括多个数据子串的数据串，使得数据子串不能单独寻址; 用于接收由数据值矩阵表示的压缩视频信息并将每个数据值按顺序加载到相应一个子串中的输入; 以及处理装置，用于通过对数据串执行一系列重新排序操作来对数据值矩阵执行逆曲折操作，以重新排列其中包括的数据子串。

公开(公告)号：US06864569B2

公开(公告)日：2005-03-08

申请号：US10714760

申请日：2003-11-17

Applicant: Paul Evans

Inventor： Paul Evans

IPC: H01L23/02 ,  H01L25/00 ,  H05K1/14

CPC classification number: H01R12/523 ,  H05K1/144

Abstract: A stackable module for a processor system including a support plate with a set of topside circuit components mounted to its topside, and topside and underside connectors. The module is stackable with other such modules and are provided with conductive tracks that are arranged to convey transport stream data and transport stream control signals between modules in a stack. A stack of such modules in a processor system is also provided.

Abstract translation: 一种用于处理器系统的可堆叠模块，其包括具有安装到其顶侧的一组顶侧电路部件的支撑板以及顶侧和下侧连接器。 该模块可与其他这样的模块堆叠并且设置有导电轨道，其被布置成在堆叠中的模块之间传送传输流数据和传输流控制信号。 还提供了处理器系统中的这种模块的堆叠。

公开(公告)号：US06859891B2

公开(公告)日：2005-02-22

申请号：US09410606

申请日：1999-10-01

Applicant: David Alan Edwards ,  Margaret Rose Gearty ,  Bernard Ramanadin ,  Anthony Willis Rich

Inventor： David Alan Edwards ,  Margaret Rose Gearty ,  Bernard Ramanadin ,  Anthony Willis Rich

IPC: G06F11/36 ,  G06F11/00

CPC classification number: G06F11/3636 ,  G06F11/3648 ,  G06F11/3656

Abstract: An microcomputer is provided including a processor and a debug circuit including a dedicated link which transfers information between the processor and debug circuit to support debugging operations. In one aspect, the processor provides program counter information, which is stored in a memory-mapped register of the debug circuit. The program counter information may be a value of the processor program counter at a writeback stage of a processor pipeline. Also, trace information including message information is transferred in a non-intrusive manner over the dedicated link. In one aspect, the microcomputer is implemented as a single integrated circuit.

Abstract translation: 提供一种包括处理器和调试电路的微计算机，该调试电路包括专用链路，该专用链路在处理器和调试电路之间传送信息以支持调试操作 在一个方面，处理器提供存储在调试电路的存储器映射寄存器中的程序计数器信息。 程序计数器信息可以是处理器管线的回写阶段处理器程序计数器的值。 此外，包括消息信息的跟踪信息通过专用链路以非侵入方式传送。 一方面，微型计算机被实现为单个集成电路。