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    ALIGNMENT APPARATUS FOR EXTERNAL PRESSURE TYPE MODULE AND FILTERING SYSTEM COMPRISING THE SAME
    171.
    发明申请
    ALIGNMENT APPARATUS FOR EXTERNAL PRESSURE TYPE MODULE AND FILTERING SYSTEM COMPRISING THE SAME 审中-公开
    用于外压式模块和包括其的过滤系统的对准装置

    公开(公告)号：US20100078374A1

    公开(公告)日：2010-04-01

    申请号：US12568164

    申请日：2009-09-28

    Applicant: Kwang-Jin Lee ,  Ah Reum Lee

    Inventor： Kwang-Jin Lee ,  Ah Reum Lee

    IPC: B01D35/30 ,  B25B27/14

    CPC classification number: B01D65/00 ,  B01D2313/06 ,  B01D2317/04 ,  Y10T29/53978

    Abstract: An alignment apparatus for external pressure type module and a filtering system comprising the same is disclosed, which is capable of supporting the external pressure type module while being connected to a pipe and the filtering system, wherein the alignment apparatus comprises a supporting member having a central through-hole into which the external pressure type module is to be inserted; and the filtering system comprises an external pressure type module, a pipe connected with the external pressure type module, and an alignment apparatus for supporting the external pressure type module while being connected with the pipe.

    Abstract translation: 公开了一种用于外部压力型模块的对准装置和包括该对置装置的过滤系统，其能够在连接到管道和过滤系统的同时支撑外部压力型模块，其中对准装置包括具有中心 要插入外压型模块的通孔; 过滤系统包括外压型模块，与外压模块连接的管道，以及用于在与管连接的同时支撑外压型模块的对准装置。

    Phase change random access memory (PRAM) device
    173.
    发明授权
    Phase change random access memory (PRAM) device 有权
    相变随机存取存储器（PRAM）设备

    公开(公告)号：US07639558B2

    公开(公告)日：2009-12-29

    申请号：US11315347

    申请日：2005-12-23

    Applicant: Beak-hyung Cho ,  Kwang-jin Lee ,  Mu-hui Park

    Inventor： Beak-hyung Cho ,  Kwang-jin Lee ,  Mu-hui Park

    IPC: G11C8/08 ,  G11C8/14

    CPC classification number: G11C11/5678 ,  G11C7/12 ,  G11C13/0004 ,  G11C13/0028 ,  G11C2213/72

    Abstract: A phase change memory device has a word line driver layout which allows for a reduction in the size a core area of the device. In one aspect, phase change memory device includes a plurality of memory cell blocks sharing a word line, and a plurality of word line drivers driving the word line. Each of the word line drivers includes a precharge device for precharging the word line and a discharge device for discharging the word line, and where the precharge device and the discharge device are alternately located between the plurality of memory cell blocks.

    Abstract translation: 相变存储器件具有字线驱动器布局，其允许减小器件的核心区域的尺寸。 一方面，相变存储器件包括共享字线的多个存储单元块和驱动该字线的多个字线驱动器。 每个字线驱动器包括用于对字线预充电的预充电装置和用于放电字线的放电装置，并且其中预充电装置和放电装置交替地位于多个存储单元块之间。

    Semiconductor device and semiconductor system having the same
    174.
    发明申请
    Semiconductor device and semiconductor system having the same 有权
    半导体器件和具有该半导体器件的半导体系统

    公开(公告)号：US20090303807A1

    公开(公告)日：2009-12-10

    申请号：US12453872

    申请日：2009-05-26

    Applicant: Kwang Jin Lee ,  Joon Min Park ,  Hye-Jin Kim

    Inventor： Kwang Jin Lee ,  Joon Min Park ,  Hye-Jin Kim

    IPC: G11C7/00 ,  G11C11/00

    CPC classification number: G11C13/0069 ,  G11C7/22 ,  G11C8/12 ,  G11C13/0004 ,  G11C2013/0076 ,  G11C2207/2209

    Abstract: A semiconductor device according to example embodiments may be configured so that, when a read command for performing a read operation is input while a write operation is performed, and when a memory bank accessed by a write address during the write operation is the same as a memory bank accessed by a read address during the read operation, the semiconductor device may suspend the write operation automatically or in response to an internal signal until the read operation is finished and performs the write operation after the read operation is finished.

    Abstract translation: 根据示例实施例的半导体器件可以被配置为使得当执行写入操作时输入用于执行读取操作的读取命令，并且当在写入操作期间由写入地址访问的存储体组与 存储体在读取操作期间由读取地址访问，半导体器件可以自动暂停写入操作或响应于内部信号直到读取操作完成，并且在读取操作完成之后执行写入操作。

    VARIABLE RESISTANCE MEMORY DEVICE AND SYSTEM
    175.
    发明申请
    VARIABLE RESISTANCE MEMORY DEVICE AND SYSTEM 有权
    可变电阻存储器件和系统

    公开(公告)号：US20090251954A1

    公开(公告)日：2009-10-08

    申请号：US12417679

    申请日：2009-04-03

    Applicant: Qi WANG ,  Kwang-Jin LEE ,  Woo-Yeong CHO ,  Taek-Sung KIM ,  Kwang-Ho KIM ,  Hyun-Ho CHOI

    Inventor： Qi WANG ,  Kwang-Jin LEE ,  Woo-Yeong CHO ,  Taek-Sung KIM ,  Kwang-Ho KIM ,  Hyun-Ho CHOI

    IPC: G11C11/00 ,  G11C8/00 ,  G11C11/416

    CPC classification number: G11C16/08 ,  G11C8/12

    Abstract: Disclosed is a semiconductor memory device including a memory cell array having a plurality of variable resistance memory cells divided into first and second areas. An I/O circuit is configured to access the memory cell array under the control of control logic so as to access the first or second area in response to an external command. The I/O circuit accesses the first area using a memory cell unit and the second area using a page unit.

    Abstract translation: 公开了一种半导体存储器件，包括具有分成第一和第二区域的多个可变电阻存储器单元的存储单元阵列。 I / O电路被配置为在控制逻辑的控制下访问存储单元阵列，以响应于外部命令访问第一或第二区域。 I / O电路使用存储单元单元访问第一区域，并且使用页面单元访问第二区域。

    NONVOLATILE MEMORY, MEMORY SYSTEM, AND METHOD OF DRIVING
    176.
    发明申请
    NONVOLATILE MEMORY, MEMORY SYSTEM, AND METHOD OF DRIVING 失效
    非易失性存储器，存储器系统和驱动方法

    公开(公告)号：US20090161419A1

    公开(公告)日：2009-06-25

    申请号：US12339204

    申请日：2008-12-19

    Applicant: Joon-Min PARK ,  Kwang-Jin Lee ,  Du-Eung Kim ,  Woo-Yeong Cho ,  Hui-Kwon Seo

    Inventor： Joon-Min PARK ,  Kwang-Jin Lee ,  Du-Eung Kim ,  Woo-Yeong Cho ,  Hui-Kwon Seo

    IPC: G11C11/00 ,  G11C11/416

    CPC classification number: G11C13/0069 ,  G11C13/0004 ,  G11C2213/72

    Abstract: Provided are a nonvolatile memory and related method of programming same. The nonvolatile memory includes a memory cell array with a plurality of nonvolatile memory cells and a write circuit. The write circuit is configured to write first logic state data to a first group of memory cells during a first program operation using a first internally generated step-up voltage, and second logic state data to a second group of memory cells during a second program operation using an externally supplied step-up voltage.

    Abstract translation: 提供了一种非易失性存储器及其相关编程方法。 非易失性存储器包括具有多个非易失性存储单元和写入电路的存储单元阵列。 写入电路被配置为在第一编程操作期间使用第一内部产生的升压电压将第一逻辑状态数据写入第一组存储器单元，并且在第二编程操作期间将第二逻辑状态数据写入第二组存储器单元 使用外部提供的升压电压。

    Non-Volatile memory device using variable resistance element with an improved write performance
    177.
    发明申请
    Non-Volatile memory device using variable resistance element with an improved write performance 有权
    使用可变电阻元件的非易失性存储器件具有改进的写入性能

    公开(公告)号：US20090154221A1

    公开(公告)日：2009-06-18

    申请号：US12314513

    申请日：2008-12-11

    Applicant: Hye-Jin Kim ,  Kwang-Jin Lee ,  Du-Eung Kim ,  Hung-Jun An

    Inventor： Hye-Jin Kim ,  Kwang-Jin Lee ,  Du-Eung Kim ,  Hung-Jun An

    IPC: G11C11/00 ,  G11C7/00 ,  G11C5/14

    CPC classification number: G11C7/1078 ,  G11C5/14 ,  G11C7/1096 ,  G11C13/00 ,  G11C13/0004 ,  G11C13/0038 ,  G11C13/0069 ,  G11C2013/009 ,  G11C2213/72

    Abstract: A non-volatile memory device using a variable resistive element is provided. The non-volatile memory device includes a memory cell array having a plurality of non-volatile memory cells, a first voltage generator generating a first voltage, a voltage pad receiving an external voltage that has a level higher than the first voltage, a sense amplifier supplied with the first voltage and reading data from the non-volatile memory cells selected from the memory cell array, and a write driver supplied with the external voltage and writing data to the non-volatile memory cells selected from the memory cell array.

    Abstract translation: 提供了使用可变电阻元件的非易失性存储器件。 非易失性存储器件包括具有多个非易失性存储器单元的存储单元阵列，产生第一电压的第一电压发生器，接收高于第一电压的电平的外部电压的电压焊盘，读出放大器 提供第一电压并从存储单元阵列中选择的非易失性存储单元读取数据，以及提供有外部电压的写入驱动器，并将数据写入从存储单元阵列中选择的非易失性存储单元。

    Semiconductor device having memory array, method of writing, and systems associated therewith
    178.
    发明申请
    Semiconductor device having memory array, method of writing, and systems associated therewith 有权
    具有存储器阵列，写入方法和与其相关联的系统的半导体器件

    公开(公告)号：US20090141567A1

    公开(公告)日：2009-06-04

    申请号：US12289937

    申请日：2008-11-07

    Applicant: Kwang Jin Lee ,  Qi Wang ,  Beak Hyung Cho

    Inventor： Kwang Jin Lee ,  Qi Wang ,  Beak Hyung Cho

    IPC: G11C7/00 ,  G11C7/22

    CPC classification number: G11C7/1078 ,  G11C7/1096 ,  G11C13/0004 ,  G11C13/0069 ,  G11C2213/72

    Abstract: In one embodiment, the semiconductor device, includes a non-volatile memory cell array, and a control unit configured to generate a mode signal indicating if a flash mode has been enabled. A write circuit is configured to write in the non-volatile memory cell array based on the mode signal such that the write circuit disables erasing the non-volatile memory cell array if the flash mode has not been enabled and instructions to erase one or more cells of the non-volatile memory cell array is received.

    Abstract translation: 在一个实施例中，半导体器件包括非易失性存储单元阵列，以及控制单元，被配置为产生指示闪光模式是否被使能的模式信号。 写电路被配置为基于模式信号写入非易失性存储单元阵列，使得如果闪存模式尚未被使能，则写电路禁止擦除非易失性存储单元阵列，并且指令擦除一个或多个单元 接收非易失性存储单元阵列。

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