Liquid crystal display
    2.
    发明授权
    Liquid crystal display 有权
    液晶显示器

    公开(公告)号:US09291868B2

    公开(公告)日:2016-03-22

    申请号:US13242875

    申请日:2011-09-23

    摘要: A liquid crystal display includes a plurality of pixels arranged in a matrix, each pixel having a first sub-pixel electrode and a second sub-pixel electrode. A first thin film transistor is connected to the first sub-pixel electrode. A second thin film transistor is connected to the second sub-pixel electrode. A third thin film transistor is connected to the second sub-pixel electrode. A fourth thin film transistor is connected to a drain electrode of the third thin film transistor. A first gate line is connected to the first thin film transistor and the second thin film transistor. A data line is connected to the first thin film transistor and the second thin film transistor. A second gate line is connected to the third thin film transistor. A third gate line is connected to the fourth thin film transistor.

    摘要翻译: 液晶显示器包括以矩阵排列的多个像素,每个像素具有第一子像素电极和第二子像素电极。 第一薄膜晶体管连接到第一子像素电极。 第二薄膜晶体管连接到第二子像素电极。 第三薄膜晶体管连接到第二子像素电极。 第四薄膜晶体管连接到第三薄膜晶体管的漏电极。 第一栅极线连接到第一薄膜晶体管和第二薄膜晶体管。 数据线连接到第一薄膜晶体管和第二薄膜晶体管。 第二栅极线连接到第三薄膜晶体管。 第三栅极线连接到第四薄膜晶体管。

    Display device and driving method thereof
    3.
    发明授权
    Display device and driving method thereof 有权
    显示装置及其驱动方法

    公开(公告)号:US09053661B2

    公开(公告)日:2015-06-09

    申请号:US13102076

    申请日:2011-05-06

    摘要: A gate-off voltage generator provides a gate-off voltage to a gate line of a display panel. The gate-off voltage generator includes a transistor having a base terminal, a collector terminal, and an emitter terminal, the emitter terminal configured to output the gate-off voltage to the gate line. A controller is connected to the base terminal. A feedback circuit is connected between the gate line and the controller, the feedback circuit configured to provide to the controller a feedback voltage based upon the gate-off voltage outputted from the emitter terminal. The gate-off voltage from the emitter terminal is compared with a desired gate-off voltage in the controller and the voltage at the base terminal is controlled by the controller to provide the desired gate-off voltage to gate line.

    摘要翻译: 栅极截止电压发生器向显示面板的栅极线提供栅极截止电压。 栅极截止电压发生器包括具有基极端子,集电极端子和发射极端子的晶体管,发射极端子被配置为将栅极截止电压输出到栅极线。 控制器连接到基本终端。 反馈电路连接在栅极线和控制器之间,反馈电路被配置为基于从发射极端子输出的栅极截止电压向控制器提供反馈电压。 将来自发射极端子的栅极截止电压与控制器中的期望栅极截止电压进行比较,并且由控制器控制基极端子处的电压,以向栅极线提供所需的栅极截止电压。

    Acid generating agent for chemically amplified resist compositions
    5.
    发明授权
    Acid generating agent for chemically amplified resist compositions 有权
    用于化学放大抗蚀剂组合物的酸产生剂

    公开(公告)号:US08779183B2

    公开(公告)日:2014-07-15

    申请号:US12214429

    申请日:2008-06-19

    IPC分类号: C07C309/17

    摘要: An acid generating agent used for chemically amplified resist compositions is provided, which agent is represented by the following formula (1): wherein X represents a monocyclic or polycyclic hydrocarbon group having 3 to 30 carbon atoms, and having at least one hydrogen atom on the ring substituted by an alkyl or alkoxy group which may be unsubstituted or substituted with a group selected from an ether group, an ester group, a carbonyl group, an acetal group, an epoxy group, a nitrile group and an aldehyde group, or by a perfluoroalkyl group, a hydroxyalkyl group, or a cyano group; R6 is an alkyl group, an alkoxy group, or a heteroatom selected from the group consisting of N, S and F; m is an integer from 0 to 2; and A+ is an organic counterion.

    摘要翻译: 提供了用于化学放大抗蚀剂组合物的酸产生剂,该试剂由下式(1)表示:其中X表示具有3至30个碳原子的单环或多环烃基,并且其上具有至少一个氢原子 可被未取代的或被选自醚基,酯基,羰基,缩醛基,环氧基,腈基和醛基中的基团取代的烷基或烷氧基取代的环,或由 全氟烷基,羟烷基或氰基; R6是烷基,烷氧基或选自N,S和F的杂原子; m为0〜2的整数; 而A +是一种有机的抗衡离子。

    Power source circuit having a protector to control an operation of a voltage generator and display apparatus having the same
    6.
    发明授权
    Power source circuit having a protector to control an operation of a voltage generator and display apparatus having the same 有权
    电源电路具有用于控制电压发生器和具有该电压发生器的显示装置的操作的保护器

    公开(公告)号:US08736593B2

    公开(公告)日:2014-05-27

    申请号:US12899848

    申请日:2010-10-07

    IPC分类号: G09G5/00

    摘要: A power source circuit of a display apparatus includes a voltage divider, an operational amplifier, a first switch, a second switch, and a protector. The voltage divider generates a divided voltage between a first driving voltage and a ground voltage. The operational amplifier receives the divided voltage and outputs the divided voltage as a second driving voltage. The first switch is connected between a first supply voltage terminal to receive the first driving voltage and a common node. The second switch is connected between the common node and a second supply voltage terminal to receive the ground voltage. The protector is connected to the common node to limit a voltage output of the first supply voltage terminal in response to a voltage of the common node.

    摘要翻译: 显示装置的电源电路包括分压器,运算放大器,第一开关,第二开关和保护器。 分压器在第一驱动电压和接地电压之间产生分压。 运算放大器接收分压,并输出分压为第二驱动电压。 第一开关连接在用于接收第一驱动电压的第一电源电压端子和公共节点之间。 第二开关连接在公共节点和第二电源电压端子之间以接收地电压。 保护器连接到公共节点,以响应于公共节点的电压来限制第一电源电压端子的电压输出。

    MEMORY DEVICE AND SYSTEM WITH IMPROVED ERASE OPERATION
    7.
    发明申请
    MEMORY DEVICE AND SYSTEM WITH IMPROVED ERASE OPERATION 有权
    具有改进的擦除操作的存储器件和系统

    公开(公告)号:US20130308370A1

    公开(公告)日:2013-11-21

    申请号:US13948138

    申请日:2013-07-22

    IPC分类号: G11C13/00

    摘要: A memory device includes a memory cell array including a plurality of memory blocks, each memory block including a plurality of memory cells, a plurality of word lines coupled to rows of the plurality of memory cells, a plurality of bit lines coupled to columns of the plurality of memory cells, and a control unit controlling an erase operation so that erase data is simultaneously written in the plurality of memory cells corresponding to an erase unit. A first erase mode may include a first erase unit and a first erase data pattern. A second erase mode may include a second erase unit and a second erase pattern. At least one of the first and second erase units and the first and second erase data patterns are different.

    摘要翻译: 存储器件包括存储单元阵列,该存储单元阵列包括多个存储器块,每个存储器块包括多个存储器单元,耦合到多个存储器单元中的行的多个字线,耦合到多个存储器单元的列的多个位线 多个存储单元,以及控制擦除操作的控制单元,使得擦除数据被同时写入与擦除单元对应的多个存储单元中。 第一擦除模式可以包括第一擦除单元和第一擦除数据模式。 第二擦除模式可以包括第二擦除单元和第二擦除模式。 第一和第二擦除单元以及第一和第二擦除数据模式中的至少一个是不同的。