公开(公告)号：US09971720B1

公开(公告)日：2018-05-15

申请号：US14724820

申请日：2015-05-29

Applicant: Netronome Systems, Inc.

Inventor： Gavin J. Stark ,  Steven W. Zagorianakos ,  Ronald N. Fortino

IPC: G06F13/40

CPC classification number: G06F13/4022 ,  G06F13/00 ,  H04L47/39 ,  H04L49/901

Abstract: An island-based integrated circuit includes a configurable mesh data bus. The data bus includes four meshes. Each mesh includes, for each island, a crossbar switch and radiating half links. The half links of adjacent islands align to form links between crossbar switches. A link is implemented as two distributed credit FIFOs. In one direction, a link portion involves a FIFO associated with an output port of a first island, a first chain of registers, and a second FIFO associated with an input port of a second island. When a transaction value passes through the FIFO and through the crossbar switch of the second island, an arbiter in the crossbar switch returns a taken signal. The taken signal passes back through a second chain of registers to a credit count circuit in the first island. The credit count circuit maintains a credit count value for the distributed credit FIFO.

公开(公告)号：US09929933B1

公开(公告)日：2018-03-27

申请号：US14841717

申请日：2015-09-01

Applicant: Netronome Systems, Inc.

Inventor： Nicolaas J. Viljoen

IPC: H04B10/00 ,  H04L12/751 ,  H04B10/27 ,  H04L29/06 ,  H04J14/00

CPC classification number: H04L45/02 ,  H04B10/27 ,  H04L43/026 ,  H04L43/0876 ,  H04L43/16

Abstract: A flow of packets is communicated through a data center. The data center includes multiple racks, where each rack includes multiple network devices. A group of packets of the flow is received onto an integrated circuit located in one of the network devices. The integrated circuit includes a neural network and a flow table. The neural network analyzes the group of packets and in response determines if it is likely that the flow has a particular characteristic. The neural network outputs a neural network output value that indicates if it is likely that the flow has a particular characteristic. The neural network output value, or a value derived from it, is included in a flow entry in the flow table on the integrated circuit. Packets of the flow subsequently received onto the integrated circuit are routed or otherwise processed according to the flow entry associated with the flow.

公开(公告)号：US09912591B1

公开(公告)日：2018-03-06

申请号：US14726421

申请日：2015-05-29

Applicant: Netronome Systems, Inc.

Inventor： Gavin J. Stark ,  Stuart C. Wray

IPC: H04L12/741 ,  H04L29/06

CPC classification number: H04L45/745 ,  G06F9/445 ,  H04L67/02 ,  H04L69/22

Abstract: An exact-match flow table structure of an integrated circuit stores flow entries. Each flow entry includes a Flow Id and an action value. Each Flow Id is a multi-bit digital value that uniquely identifies a flow. A Flow Id does not include any wildcard indictor. The flow table structure cannot and does not store an indicator that any particular part of a packet should be matched against any part of a Flow Id. In one example, a packet is received onto the integrated circuit. A Flow Id is generated from the packet. If the flow table structure determines that the Flow Id is a bit-by-bit exact-match of any Flow Id of any stored flow entry, then the packet is handled according to the action value of the flow entry. If, on the other hand, there is not exact-match, then a miss indication is output from the integrated circuit.

公开(公告)号：US09887918B1

公开(公告)日：2018-02-06

申请号：US14530762

申请日：2014-11-02

Applicant: Netronome Systems, Inc.

Inventor： Gavin J. Stark

IPC: G06F9/30 ,  H04L12/741

CPC classification number: H04L49/90

Abstract: A multi-processor includes a pool of processors and a common packet buffer memory. Bytes of packet data of a packet are stored in the packet buffer memory. Each of the processors has an intelligent packet data register file. One processor is tasked with processing the packet data, and its packet data register file caches a subset of the bytes of packet data. Some instructions when executed require that the packet data register file supply the execute stage of the processor with certain bytes of the packet data. If during instruction execution the intelligent packet data register file determines that it does not store some of the necessary bytes, then the register file asserts a stall signal thereby stalling the processor, and retrieves the bytes from the packet buffer memory, and then supplies the retrieved bytes to the execute stage, and de-asserts the stall signal to unstall the processor.

公开(公告)号：US09854072B1

公开(公告)日：2017-12-26

申请号：US14818070

申请日：2015-08-04

Applicant: Netronome Systems, Inc.

Inventor： Chirag P. Patel ,  Gavin J. Stark

IPC: H04L29/06 ,  H04L12/935

CPC classification number: H04L69/22 ,  G06F9/00 ,  G06F9/30018 ,  G06F9/3867 ,  H04L49/3063 ,  H04L69/04

Abstract: An egress packet modifier includes a script parser and a pipeline of processing stages. Rather than performing egress modifications using a processor that fetches and decodes and executes instructions in a classic processor fashion, and rather than storing a packet in memory and reading it out and modifying it and writing it back, the packet modifier pipeline processes the packet by passing parts of the packet through the pipeline. A processor identifies particular egress modifications to be performed by placing a script code at the beginning of the packet. The script parser then uses the code to identify a specific script of opcodes, where each opcode defines a modification. As a part passes through a stage, the stage can carry out the modification of such an opcode. As realized using current semiconductor fabrication process, the packet modifier can modify 200M packets/second at a sustained rate of up to 100 gigabits/second.

公开(公告)号：US09804976B1

公开(公告)日：2017-10-31

申请号：US14841300

申请日：2015-08-31

Applicant: Netronome Systems, Inc.

Inventor： Gavin J. Stark ,  Johann H. Tönsing

IPC: G06F12/14 ,  G06F9/46

CPC classification number: G06F12/1466 ,  G06F9/467 ,  G06F17/30 ,  G06F17/30362 ,  G06F2212/1052

Abstract: A transactional memory (TM) receives an Atomic Look-up, Add and Lock (ALAL) command across a bus from a client. The command includes a first value. The TM pulls a second value. The TM uses the first value to read a set of memory locations, and determines if any of the locations contains the second value. If no location contains the second value, then the TM locks a vacant location, adds the second value to the vacant location, and sends a result to the client. If a location contains the second value and it is not locked, then the TM locks the location and returns a result to the client. If a location contains the second value and it is locked, then the TM returns a result to the client. Each location has an associated data structure. Setting the lock field of a location locks access to its associated data structure.

公开(公告)号：US09755983B1

公开(公告)日：2017-09-05

申请号：US14521435

申请日：2014-10-22

Applicant: Netronome Systems, Inc.

Inventor： Ron Lamar Swartzentruber

IPC: H04L12/801

CPC classification number: H04L47/39

Abstract: An apparatus and method for providing minipacket flow control. A device includes a traffic manager interface (TMI) circuit that receives a minipacket, communicates the minipacket to a physical layer circuit, and communicates a minipacket flow control signal to a scheduler circuit that controls if another minipacket is to be sent to the TMI circuit. In one example, upon receiving a minipacket the TMI circuit updates a current credit value, compares the current credit value with a credit limit value, and outputs a minipacket flow control signal that is a function of the comparison. In another example, upon receiving a minipacket the TMI circuit updates a current credit value, compares the current credit value with a credit limit value, reads and compares a credit pool value with a credit pool limit value, and outputs a minipacket flow control signal that is a function of both of the comparisons.

公开(公告)号：US09755948B1

公开(公告)日：2017-09-05

申请号：US14841723

申请日：2015-09-01

Applicant: Netronome Systems, Inc.

Inventor： Nicolaas J. Viljoen

IPC: H04J14/00 ,  H04L12/801 ,  H04L12/751 ,  H04Q11/00 ,  H04L12/851 ,  H04L12/24

CPC classification number: H04L45/08 ,  H04L41/0823 ,  H04L41/083 ,  H04L41/14 ,  H04L41/16 ,  H04L45/10 ,  H04L47/2483 ,  H04Q11/00 ,  H04Q11/0005 ,  H04Q11/0066 ,  H04Q2011/0079 ,  H04Q2213/13523

Abstract: A flow of packets is communicated through a data center including an electrical switch, an optical switch, and multiple racks each including multiple network devices. The optical switch can be controlled to receive packet traffic from a network device via a first optical link and to output that packet traffic to another network device via a second optical link. One network device includes a neural network that analyzes received packets of the flow. The optical switch is controlled to switch based on a result of the analysis performed. In one instance, the optical switch is controlled such that immediately prior to the switching no packet traffic passes from the first optical link and through the optical switch and to the second optical link but such that after the switching packet traffic does pass from the first optical link and through the optical switch and to the second optical link.

公开(公告)号：US09729442B1

公开(公告)日：2017-08-08

申请号：US14634848

申请日：2015-03-01

Applicant: Netronome Systems, Inc.

Inventor： Gavin J. Stark ,  Stuart C. Wray

IPC: H04L12/741 ,  H04L12/931 ,  H04L12/947

CPC classification number: H04L45/745 ,  H04L45/54 ,  H04L49/25 ,  H04L49/35

Abstract: A method of Software-Defined Networking (SDN) switching. A packet of a flow is received onto a SDN switch via a NFX circuit. The NFX circuit determines that the packet matches a flow entry stored in any flow table in the NFX circuit, counts the number of packets of the flow received, and determines that the number of packets of the flow received is above a threshold value. The NFX circuit then forwards the packet to a NFP circuit in the SDN switch. The NFP circuit determines that the packet matches a flow entry stored in the flow table in the NFX and generates a new flow entry that applies to a relatively narrow subflow of packets that is forwarded to and stored the flow table in the NFX circuit. A subsequent packet of the flow is switched by the SDN switch without forwarding the packet to the NFP.

公开(公告)号：US09727512B1

公开(公告)日：2017-08-08

申请号：US14530758

申请日：2014-11-02

Applicant: Netronome Systems, Inc.

Inventor： Ron Lamar Swartzentruber

IPC: G06F13/36 ,  G06F13/40 ,  G06F3/06

CPC classification number: G06F13/4027 ,  G06F3/0613 ,  G06F3/0647 ,  G06F3/0683

Abstract: A method of performing an identical packet multicast packet ready command (common packet multicast mode operation) is described herein. A packet ready command is received from a first memory system via a bus and onto a network interface circuit. The packet ready command includes a multicast value. A communication mode is determined as a function of the multicast value. The multicast value indicates a single packet is to be communicated by the network interface circuit to a first number of destinations. A free packet command is output from the network interface circuit onto the bus. The free packet command includes a Free On Last Transfer (FOLT) value that indicates that the packet will not be freed from the first memory system by the network interface circuit once the packet is transmitted. The network interface circuit and the memory system are included on an Island-Based Network Flow Processor.