Abstract:
A split-gate non-volatile memory device includes a raised oxide layer on a field oxide region between adjacent split-gate memory cells, the raised oxide layer extending onto first and second floating gates included in the adjacent split-gate memory cells covered by a wordline electrically coupled to respective control gates included in the adjacent split-gate memory cells.
Abstract:
The present invention discloses a home network system (1) which can provide an efficient address system for home appliances by using a dynamic address field selectively including at least two different kinds of logical address codes. The home network system (1) includes at least one slave device (40), and a master device (30) connected to the slave devices (40) through a predetermined network (20), the master device (30) and the slave device (40) distinguishing each other by an address field including a dynamic address field selectively having at least two different kinds of logical address codes to distinguish a plurality of slave devices (40) and master devices (30).
Abstract:
The present invention discloses a home network system (100) which uses a message structure for efficient communication between a plurality of home appliances. The home network system (100) includes at least one slave device (60, 70, 80), and at least one master device (50) connected to the slave device (60, 70, 80) through a network (90), for transmitting a request message to the slave device (60, 70, 80), wherein the request message is transmitted from an upper layer of the master device (50) to a lower layer thereof and from a lower layer of the slave device (60, 70, 80) to an upper layer thereof, and has a command code implying an operation which will be executed by the slave device (60, 70, 80), and a related argument for executing the operation.
Abstract:
A semiconductor device capable of suppressing void migration is provided. The semiconductor device includes a dummy region extending in a first direction substantially perpendicular to a second direction in which a word line extends. In addition, an isolation layer pattern may not cut the dummy region in the second direction. Consequently, leaning of the dummy region and void migration are prevented. A method of fabricating the semiconductor device is also provided.
Abstract:
Embodiments of a profile motor are provided. A spindle motor can include a base in contact with a bearing housing, a bearing installed in the bearing housing, a rotational shaft rotatably supported by the bearing, a stator disposed around the bearing housing and having a coil, a rotor including a rotor yoke fixed on the rotational shaft and a magnet fixed on the rotor yoke, a turntable provided above the rotor yoke and rotating together with the rotational shaft, and a plurality of balls provided in a space defined by the rotor yoke and the turntable.
Abstract:
a nonvolatile memory device Includes an active region defined in a semiconductor substrate and a control gate electrode crossing over the active region. A gate insulating layer is interposed between the control gate electrode and the active reigon. A floating gate is formed in the active region to penetrate the control gate electrode and extend to a predetermined depth into the semiconductor substrate. A tunnel insulating layer is successively interposed between the control gate electrode and the floating gate, and between the semiconductor substrate and the floating gate. The floating gate may be formed after a trench is formed by sequentially etching a control gate conductive layer and the semiconductor substrate, and a tunnel insulating layer is formed on the trench and sidewalls of the control gate conductive layer. The floating gate is formed in the trench to extend into a predetermined depth into the semiconductor substrate.
Abstract:
The present invention discloses an upgrade apparatus and its method for a home network system which can automatically upgrade software. The upgrade apparatus for the home network system is installed in the home network system having a first storage unit in which at least one protected program has been installed, and includes n upgrade means for deciding whether a second storage unit separated from the first storage unit stores an upgrade file corresponding to the protected program, and upgrading the protected program by using the upgrade file according to the decision result.
Abstract:
The present invention relates to a high voltage transistor and method of manufacturing the same. The high voltage transistor includes: a channel region which is formed in a semiconductor substrate; a gate insulating film which is formed on the channel region of the semiconductor substrate; a low concentration source region and a low concentration drain region having the channel region interposed therebetween and each being formed in the semiconductor substrate; a high concentration source region which is formed to be spaced away from the channel region by a first distance; a high concentration drain region which is formed to be spaced away from the channel region by a second distance that is larger than the first distance; a gate electrode which has a gate bottom portion interfacing with the gate insulating film over the channel region, and a gate top portion integrated with the gate bottom portion and protruding by a predetermined length from a top of the gate bottom portion to extend over the low concentration drain region; a first metal silicide layer which is formed on the high concentration source region; and a second metal silicide layer which is formed on the high concentration drain region.
Abstract:
A flash memory device including a tunnel dielectric layer, a floating gate layer, an interlayer dielectric layer and at least two mold layers formed on a semiconductor substrate and a method of manufacturing the same are provided. By sequentially patterning the layers, a first mold layer pattern and a floating gate layer pattern aligned with each other are formed. Exposed portions of side surfaces of the first mold layer pattern are selectively lateral etched, thereby forming a first mold layer second pattern having grooves in its sidewalls. A gate dielectric layer is formed on the semiconductor substrate adjacent to the floating gate layer pattern. A control gate having a width that is determined by the grooves in the second mold layer pattern is formed on the gate dielectric layer. By removing the first mold layer second pattern, spacers are formed on sidewalls of the control gate. Exposed portions of the interlayer dielectric layer and the floating gate layer pattern are selectively etched, using the spacer as an etch mask to form a floating gate having a width defined by the widths of the groove and spacer.
Abstract:
An apparatus for providing duplicated shelf managers in an ATCA system is provided. The apparatus for providing duplicated shelf managers includes a hub/switch in a control backplane to allow a manager to access the duplicated shelf managers all the time from an external network while maintaining the switch configuration defined of the ATCA specification. The hub/switch connects Ethernet ports of the duplicated two shelf managers and Ethernet ports of the two switches at the same time, and connects the two shelf managers and the two switches to the Internet.