公开(公告)号：US07827473B2

公开(公告)日：2010-11-02

申请号：US11811014

申请日：2007-06-07

申请人： Tak K. Lee ,  Ba-Zhong Shen

发明人： Tak K. Lee ,  Ba-Zhong Shen

IPC分类号： H03M13/03

CPC分类号： G06F11/1008 ,  H03M13/2753 ,  H03M13/2775 ,  H03M13/2957 ,  H03M13/3905 ,  H03M13/3972

摘要： Turbo decoder employing ARP (almost regular permutation) interleave and arbitrary number of decoding processors. A novel approach is presented herein by which an arbitrarily selected number (M) of decoding processors (e.g., a plurality of parallel implemented turbo decoders) be employed to perform decoding of a turbo coded signal while still using a selected embodiment of an ARP (almost regular permutation) interleave. The desired number of decoding processors is selected, and very slight modification of an information block (thereby generating a virtual information block) is made to accommodate that virtual information block across all of the decoding processors during all decoding cycles except some dummy decoding cycles. In addition, contention-free memory mapping is provided between the decoding processors (e.g., a plurality of turbo decoders) and memory banks (e.g., a plurality of memories).

摘要翻译： Turbo解码器采用ARP（几乎规则排列）交错和任意数量的解码处理器。 本文提出了一种新颖的方法，通过该方法，使用任意选择的数量（M）的解码处理器（例如，多个并行实现的turbo解码器）来执行turbo编码信号的解码，同时仍然使用所选择的ARP实施例（几乎 正则排列）交错。 选择所需数量的解码处理器，并且进行信息块（从而生成虚拟信息块）的非常轻微的修改以在除了一些虚拟解码周期之外的所有解码周期期间在所有解码处理器之间容纳该虚拟信息块。 此外，在解码处理器（例如，多个turbo解码器）和存储体（例如，多个存储器）之间提供无竞争的存储器映射。

公开(公告)号：US20090199062A1

公开(公告)日：2009-08-06

申请号：US12362543

申请日：2009-01-30

申请人： Ba-Zhong Shen ,  Sirikiat Lek Ariyavisitakul ,  Tak K. Lee

发明人： Ba-Zhong Shen ,  Sirikiat Lek Ariyavisitakul ,  Tak K. Lee

IPC分类号： H04L1/18 ,  H03M13/23 ,  G06F11/14 ,  G06F11/08

CPC分类号： H03M13/2957 ,  H03M13/2739 ,  H03M13/6306 ,  H03M13/6356 ,  H03M13/6362 ,  H03M13/653 ,  H04L1/005 ,  H04L1/0066 ,  H04L1/0067 ,  H04L1/1819

摘要： Virtual limited buffer modification for rate matching. A reduced-size memory module is employed within a communication device to assist in storage of log-likelihood ratios (LLRs) employed in accordance with turbo decoding. This architecture is also applicable to other types of error correction code (ECC) besides turbo code as well. The memory size is selected to match the number of coded bits (e.g., including information bits and redundancy/parity bits) that is included within a transmission. The received signals may be various transmissions made in accordance with hybrid automatic repeat request (HARQ) transmissions. When the LLRs calculated from a first HARQ transmission is insufficient to decode, those LLRs are selectively stored in the memory module. When LLRs corresponding to a second HARQ transmission is received, LLRs corresponding to both the first HARQ transmission and the second HARQ transmission are passed from the memory module for joint use in decoding.

摘要翻译： 用于速率匹配的虚拟限制缓冲区修改。 在通信设备内采用缩小尺寸的存储器模块以帮助存储根据turbo解码所采用的对数似然比（LLR）。 该架构也适用于除turbo码之外的其他类型的纠错码（ECC）。 选择存储器大小以匹配包含在传输内的编码比特数（例如，包括信息比特和冗余/奇偶校验比特）。 所接收的信号可以是根据混合自动重传请求（HARQ）传输而进行的各种传输。 当从第一HARQ传输计算的LLR不足以解码时，那些LLR被选择性地存储在存储器模块中。 当接收到对应于第二HARQ传输的LLR时，对应于第一HARQ传输和第二HARQ传输两者的LLR从存储器模块传递以用于解码。

公开(公告)号：US20090119568A1

公开(公告)日：2009-05-07

申请号：US12261572

申请日：2008-10-30

申请人： Ba-Zhong Shen ,  Tak K. Lee

发明人： Ba-Zhong Shen ,  Tak K. Lee

IPC分类号： H03M13/15 ,  G06F11/10

CPC分类号： H03M13/09 ,  H04L1/0057 ,  H04L1/0066

摘要： Single CRC polynomial for both turbo code block CRC and transport block CRC. Rather than employing multiple and different generation polynomials for generating CRC fields for different levels within a coded signal, a single CRC polynomial is employed for the various levels. Effective error correction capability is achieved with minimal hardware requirement by using a single CRC polynomial for various layers of CRC encoding. Such CRC encoding can be implemented within any of a wide variety of communication devices that may be implemented within a wide variety of communication systems (e.g., a satellite communication system, a wireless communication system, a wired communication system, and a fiber-optic communication system, etc.). In addition, a single CRC check can be employed within a receiver (or transceiver) type communication device for each of the various layers of CRC of a received signal.

摘要翻译： 用于turbo码块CRC和传输块CRC的单个CRC多项式。 不是采用多个不同的生成多项式来生成用于编码信号内的不同级别的CRC字段，而是针对各种级别使用单个CRC多项式。 通过对CRC编码的各个层使用单个CRC多项式，以最小的硬件要求实现了有效的纠错能力。 这种CRC编码可以在可以在各种各样的通信系统（例如，卫星通信系统，无线通信系统，有线通信系统和光纤通信）中实现的各种通信设备中的任何一种内实现 系统等）。 此外，对于接收信号的CRC的各个层中的每一个，可以在接收机（或收发器）类型通信设备内采用单个CRC校验。

公开(公告)号：US20080086674A1

公开(公告)日：2008-04-10

申请号：US11811013

申请日：2007-06-07

申请人： Ba-Zhong Shen ,  Tak K. Lee

发明人： Ba-Zhong Shen ,  Tak K. Lee

IPC分类号： H03M13/05

CPC分类号： H03M13/2978 ,  H03M13/2775 ,  H03M13/296 ,  H03M13/6516 ,  H03M13/6525 ,  H03M13/6561

摘要： Reduced complexity ARP (almost regular permutation) interleaves providing flexible granularity and parallelism adaptable to any possible turbo code block size. A novel means is presented by which any desired turbo code block size can be employed when only requiring, in only some instances, a very small number of dummy bits. This approach also is directly adaptable to parallel turbo decoding, in which any desired degree of parallelism can be employed. Alternatively, as few as one turbo decoder can be employed in a fully non-parallel implementation as well. Also, this approach allows for storage of a reduced number of parameters to accommodate a wide variety of interleaves.

摘要翻译： 降低复杂度ARP（几乎规则排列）交错，提供适应任何可能的turbo码块大小的灵活的粒度和并行性。 提出了一种新颖的方法，当仅需要非常少量的虚拟位时，可以采用任何期望的turbo码块大小。 这种方法也可直接适用于平行turbo解码，其中可以采用任何期望的并行度。 或者，也可以在完全非并行实现中使用少至一个turbo解码器。 此外，该方法允许存储少量参数以适应各种各样的交错。

公开(公告)号：US09231616B2

公开(公告)日：2016-01-05

申请号：US13523818

申请日：2012-06-14

申请人： Brian Heng ,  Ba-Zhong Shen

发明人： Brian Heng ,  Ba-Zhong Shen

IPC分类号： H04N7/12 ,  H04N11/02 ,  H04N11/04 ,  H03M7/40 ,  H04N19/91 ,  H04N19/13 ,  H04N19/156

CPC分类号： H03M7/4006 ,  H03M7/40 ,  H03M7/4018 ,  H04N19/13 ,  H04N19/156 ,  H04N19/91

摘要： Unified binarization for CABAC/CAVLC entropy coding. Scalable entropy coding is implemented in accordance with any desired degree of complexity (e.g., entropy encoding and/or decoding). For example, appropriately implemented context-adaptive variable-length coding (CAVLC) and context-adaptive binary arithmetic coding (CABAC) allow for selective entropy coding in accordance with a number of different degrees of complexity. A given device may operate in accordance with a first level complexity a first time, a second level complexity of the second time, and so on. Appropriate coordination and signaling between an encoder/transmitter device and a decoder/receiver device allows for appropriate coordination along a desired degree of complexity. For example, a variable length binarization module and an arithmetic encoding module may be implemented within an encoder/transmitter device and a corresponding arithmetic decoding module and a variable length bin decoding module may be implemented within a decoder/receiver device allowing for entropy coding along various degrees of complexity.

公开(公告)号：US08433971B2

公开(公告)日：2013-04-30

申请号：US12770068

申请日：2010-04-29

申请人： Andrew J. Blanksby ,  Ba-Zhong Shen ,  Jason A. Trachewsky

发明人： Andrew J. Blanksby ,  Ba-Zhong Shen ,  Jason A. Trachewsky

IPC分类号： H03M13/00

CPC分类号： H03M13/1102 ,  H03M13/033 ,  H03M13/1134 ,  H03M13/1137 ,  H03M13/116 ,  H03M13/1185 ,  H03M13/1188 ,  H03M13/618 ,  H03M13/6362 ,  H03M13/6393 ,  H03M13/6502 ,  H03M13/6516 ,  H03M13/6527 ,  H04L1/005 ,  H04L1/0057

摘要： Communication device architecture for in-place constructed LDPC (Low Density Parity Check) code. Intelligent design of LDPC codes having similar characteristics there between allows for a very efficient hardware implementation of a communication device that is operative to perform encoding of respective information bit groups using more than one type of LDPC codes. A switching module can select any one of the LDPC codes within an in-place LDPC code for use by an LDPC encoder circuitry to generate an LDPC coded signal. Depending on which sub-matrices of a superimposed LDPC matrix are enabled or disabled, one of the LDPC matrices from within an in-place LDPC code matrix set may be selected. A corresponding, respective generator matrix may be generated from each respective LDPC matrix. Selection among the various LDPC codes may be in accordance with a predetermined sequence, of based operating conditions of the communication device or communication system.

摘要翻译： 用于就地构造的LDPC（低密度奇偶校验）码的通信设备架构。 具有相似特性的LDPC码的智能设计允许通信设备的非常有效的硬件实现，该通信设备可操作以使用多于一种类型的LDPC码执行各个信息位组的编码。 交换模块可以在就地LDPC码内选择任何一个LDPC码，供LDPC编码器电路使用以产生LDPC编码信号。 根据叠加的LDPC矩阵的哪些子矩阵被使能或禁用，可以选择来自就地内LDPC码矩阵集合的LDPC矩阵之一。 可以从每个相应的LDPC矩阵生成相应的相应的生成器矩阵。 各种LDPC码之间的选择可以与通信设备或通信系统的基于操作条件的预定顺序相一致。

公开(公告)号：US20130077697A1

公开(公告)日：2013-03-28

申请号：US13523830

申请日：2012-06-14

申请人： Peisong Chen ,  Ba-Zhong Shen ,  Wade K. Wan

发明人： Peisong Chen ,  Ba-Zhong Shen ,  Wade K. Wan

IPC分类号： H04N7/26

CPC分类号： H04N19/82 ,  H04N19/117 ,  H04N19/147 ,  H04N19/174 ,  H04N19/176 ,  H04N19/46 ,  H04N19/61

摘要： Adaptive loop filtering in accordance with video coding. An adaptive loop filter (ALF) and/or other in-loop filters (e.g., sample adaptive offset (SAO) filter, etc.) may be implemented within various video coding architectures (e.g., encoding and/or decoding architectures) to perform both offset and scaling processing, only scaling processing, and/or only offset processing. Operation of such an ALF may be selective in accordance with any of multiple respective operational modes at any given time and may be adaptive based upon various consideration(s) (e.g., desired complexity level, processing type, local and/or remote operational conditions, etc.). For example, an ALF may be applied to a decoded picture before it is stored in a picture buffer (or digital teacher buffer (DPB)). An ALF can provide for coding noise reduction of a decoded picture, and the filtering operations performed thereby may be selective (e.g., on a slice by slice basis, block by block basis, etc.).

摘要翻译： 根据视频编码进行自适应环路滤波。 可以在各种视频编码架构（例如，编码和/或解码架构）内实现自适应环路滤波器（ALF）和/或其他环路滤波器（例如，采样自适应偏移（SAO）滤波器等）以执行两者 偏移和缩放处理，仅缩放处理和/或仅偏移处理。 这种ALF的操作可以根据任何给定时间的多个相应的操作模式中的任何一个来选择，并且可以基于各种考虑（例如，期望的复杂性水平，处理类型，本地和/或远程操作条件， 等等。）。 例如，可以将ALF存储在图像缓冲器（或数字教师缓冲器（DPB））中之前将其应用于解码图像。 ALF可以提供解码图像的编码噪声降低，并且由此执行的滤波操作可以是选择性的（例如，逐个逐个基础，逐个基础地等）。

公开(公告)号：US08301967B2

公开(公告)日：2012-10-30

申请号：US12843558

申请日：2010-07-26

申请人： Ravi Bhaskaran ,  Bruce J. Currivan ,  Thomas J. Kolze ,  Ba-Zhong Shen

发明人： Ravi Bhaskaran ,  Bruce J. Currivan ,  Thomas J. Kolze ,  Ba-Zhong Shen

IPC分类号： G06F11/00

CPC分类号： H04N21/437 ,  H03M13/29 ,  H03M13/2957 ,  H03M13/2966 ,  H03M13/6511 ,  H04L12/2801 ,  H04N7/17309

摘要： A method of transmitting data in a cable modem system includes the steps of encoding the data using forward error correction. The data is then encoded with Turbo encoding. The data is then sent to a modulation scheme. The data is then transmitted over a cable channel. The data is then demodulated. The data is then decoded using a Turbo decoder. An inverse of the forward error correction is then applied to the data.

摘要翻译： 在电缆调制解调器系统中发送数据的方法包括使用前向纠错对数据进行编码的步骤。 然后使用Turbo编码对数据进行编码。 然后将数据发送到调制方案。 然后通过有线信道传输数据。 然后解调数据。 然后使用Turbo解码器对数据进行解码。 然后将前向纠错的逆向应用于数据。

公开(公告)号：US20120106640A1

公开(公告)日：2012-05-03

申请号：US12945949

申请日：2010-11-15

申请人： Ba-Zhong Shen ,  Brian Heng

发明人： Ba-Zhong Shen ,  Brian Heng

IPC分类号： H04N7/12

CPC分类号： H04N19/198 ,  H04N19/11 ,  H04N19/176 ,  H04N19/44 ,  H04N19/463

摘要： Decoding side intra-prediction derivation for video coding. Just decoded pixels within a given picture (image) (e.g., such as a given picture (image) within video data) are employed for decoding other pixels within that very same picture (image) using prediction vectors extending from the just decoded pixels to the pixels currently being decoded. In one instance, this intra-prediction operation in accordance with video or image processing can also operate using relatively limited information provided from the device that provides or transmits the video data to the device in which it undergoes processing. Coarse and/or refined direction information corresponding to these prediction vectors may be provided from the device that provides or transmits the video data to the device in which it undergoes processing.

摘要翻译： 用于视频编码的解码侧帧内预测推导。 使用给定图像（图像）内的解码像素（例如，视频数据中的给定图像（图像））来解码使用从刚刚解码的像素延伸到相同图像的图像（图像）内的其他像素 当前正在解码的像素。 在一种情况下，根据视频或图像处理的该帧内预测操作也可以使用从提供或发送视频数据到其进行处理的设备的设备提供的相对有限的信息来进行操作。 可以从提供或发送视频数据到其进行处理的设备的设备提供对应于这些预测向量的粗略和/或精细方向信息。

公开(公告)号：US20100115372A1

公开(公告)日：2010-05-06

申请号：US12612648

申请日：2009-11-04

申请人： Jason A. Trachewsky ,  Ba-Zhong Shen

发明人： Jason A. Trachewsky ,  Ba-Zhong Shen

IPC分类号： H03M13/05 ,  G06F11/10

CPC分类号： H03M13/1102 ,  H03M13/6356 ,  H03M13/6362 ,  H04L1/0068 ,  H04L1/0079 ,  H04L1/08 ,  H04L27/2601

摘要： Header encoding for SC and/or OFDM signaling using shortening, puncturing, and/or repetition in accordance with encoding header information within a frame to be transmitted via a communication channel employs different respective puncturing patterns as applied to different portions thereof. For example, a first puncturing pattern is applied to a first portion of the frame, and a second puncturing pattern is applied to a second portion of the frame (the second portion may be a repeated version of the first portion). Shortening (e.g., by padding 0-valued bits thereto) may be made to header information bits before they undergo encoding (e.g., in an LDPC encoder). One or both of the information bits and parity/redundancy bits output from the encoder undergo selective puncturing. Moreover, one or both of the information bits and parity/redundancy bits output from the encoder may be repeated/spread before undergoing selective puncturing to generate a header.

摘要翻译： 根据要通过通信信道发送的帧内的编码头信息，使用缩短，删截和/或重复的SC和/或OFDM信令的报头编码，采用不同的相应的打孔图案，应用于其不同部分。 例如，将第一穿孔图案应用于框架的第一部分，并且将第二穿孔图案应用于框架的第二部分（第二部分可以是第一部分的重复版本）。 在进行编码之前（例如，在LDPC编码器中），可以缩短（例如，通过填充0值比特）到头信息比特。 从编码器输出的信息位和奇偶校验/冗余位中的一个或两个进行选择性穿孔。 此外，可以在进行选择性穿孔之前重复/扩展从编码器输出的信息比特和奇偶校验/冗余比特中的一个或两个以产生报头。