公开(公告)号：US11121030B2

公开(公告)日：2021-09-14

申请号：US16473960

申请日：2017-03-30

Applicant: INTEL CORPORATION

Inventor： Glenn A. Glass ,  Anand S. Murthy ,  Karthik Jambunathan ,  Benjamin Chu-Kung ,  Seung Hoon Sung ,  Jack T. Kavalieros ,  Tahir Ghani

IPC: H01L21/768 ,  H01L29/06 ,  H01L29/08 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78 ,  H01L29/423 ,  H01L29/49

Abstract: Techniques are disclosed for forming transistors employing a carbon-based etch stop layer (ESL) for preserving source and drain (S/D) material during contact trench etch processing. As can be understood based on this disclosure, carbon-based layers can provide increased resistance for etch processing, such that employing a carbon-based ESL on S/D material can preserve that S/D material during contact trench etch processing. This is due to carbon-based layers being able to provide more robust (e.g., more selective) etch selectivity during contact trench etch processing than the S/D material it is preserving (e.g., Si, SiGe, Ge, group III-V semiconductor material) and other etch stop layers (e.g., insulator material-based etch stop layers). Employing a carbon-based ESL enables a given S/D region to protrude from shallow trench isolation (STI) material prior to contact metal deposition, thereby providing more surface area for making contact to the given S/D region, which improves transistor performance.

公开(公告)号：US11101356B2

公开(公告)日：2021-08-24

申请号：US16641032

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Glenn A. Glass ,  Anand S. Murthy ,  Karthik Jambunathan ,  Cory C. Bomberger ,  Tahir Ghani ,  Jack T. Kavalieros ,  Benjamin Chu-Kung ,  Seung Hoon Sung ,  Siddharth Chouksey

IPC: H01L29/40 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/16 ,  H01L29/417 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786

Abstract: Integrated circuit transistor structures are disclosed that reduce n-type dopant diffusion, such as phosphorous or arsenic, from the source region and the drain region of a germanium n-MOS device into adjacent insulator regions during fabrication. The n-MOS transistor device may include at least 75% germanium by atomic percentage. In an example embodiment, a dopant-rich insulator cap is deposited adjacent to the source and/or drain regions, to provide dopant diffusion reduction. In some embodiments, the dopant-rich insulator cap is doped with an n-type impurity including Phosphorous in a concentration between 1 and 10% by atomic percentage. In some embodiments, the dopant-rich insulator cap may have a thickness in the range of 10 to 100 nanometers and a height in the range of 10 to 200 nanometers.

公开(公告)号：US10930500B2

公开(公告)日：2021-02-23

申请号：US16431646

申请日：2019-06-04

Applicant: Intel Corporation

Inventor： Sansaptak Dasgupta ,  Han Wui Then ,  Benjamin Chu-Kung ,  Marko Radosavljevic ,  Sanaz K. Gardner ,  Seung Hoon Sung ,  Ravi Pillarisetty ,  Robert S. Chau

IPC: H01L21/02 ,  H01L29/778 ,  H01L29/04 ,  H01L29/06 ,  H01L29/20 ,  H01L21/8252 ,  H01L27/06 ,  H01L29/16 ,  H01L29/267 ,  H01L29/78 ,  H01L29/66

Abstract: III-N semiconductor heterostructures including a raised III-N semiconductor structures with inclined sidewall facets are described. In embodiments, lateral epitaxial overgrowth favoring semi-polar inclined sidewall facets is employed to bend crystal defects from vertical propagation to horizontal propagation. In embodiments, arbitrarily large merged III-N semiconductor structures having low defect density surfaces may be overgrown from trenches exposing a (100) surface of a silicon substrate. III-N devices, such as III-N transistors, may be further formed on the raised III-N semiconductor structures while silicon-based transistors may be formed in other regions of the silicon substrate.

公开(公告)号：US20210005722A1

公开(公告)日：2021-01-07

申请号：US16641032

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Glenn A. Glass ,  Anand S. Murthy ,  Karthik Jambunathan ,  Cory C. Bomberger ,  Tahir Ghani ,  Jack T. Kavalieros ,  Benjamin Chu-Kung ,  Seung Hoon Sung ,  Siddharth Chouksey

IPC: H01L29/40 ,  H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L29/16 ,  H01L29/10 ,  H01L29/417 ,  H01L29/423 ,  H01L29/786 ,  H01L27/092 ,  H01L21/02 ,  H01L21/8238

Abstract: Integrated circuit transistor structures are disclosed that reduce n-type dopant diffusion, such as phosphorous or arsenic, from the source region and the drain region of a germanium n-MOS device into adjacent insulator regions during fabrication. The n-MOS transistor device may include at least 75% germanium by atomic percentage. In an example embodiment, a dopant-rich insulator cap is deposited adjacent to the source and/or drain regions, to provide dopant diffusion reduction. In some embodiments, the dopant-rich insulator cap is doped with an n-type impurity including Phosphorous in a concentration between 1 and 10% by atomic percentage. In some embodiments, the dopant-rich insulator cap may have a thickness in the range of 10 to 100 nanometers and a height in the range of 10 to 200 nanometers.

公开(公告)号：US10748993B2

公开(公告)日：2020-08-18

申请号：US16524529

申请日：2019-07-29

Applicant: Intel Corporation

Inventor： Van H. Le ,  Benjamin Chu-Kung ,  Harold Hal W. Kennel ,  Willy Rachmady ,  Ravi Pillarisetty ,  Jack T. Kavalieros

IPC: H01L29/06 ,  H01L21/02 ,  H01L29/786 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L21/283 ,  H01L29/10 ,  H01L29/165 ,  H01L29/15 ,  H01L29/161 ,  H01L29/08

Abstract: Transistor structures having channel regions comprising alternating layers of compressively and tensilely strained epitaxial materials are provided. The alternating epitaxial layers can form channel regions in single and multigate transistor structures. In alternate embodiments, one of the two alternating layers is selectively etched away to form nanoribbons or nanowires of the remaining material. The resulting strained nanoribbons or nanowires form the channel regions of transistor structures. Also provided are computing devices comprising transistors comprising channel regions comprised of alternating compressively and tensilely strained epitaxial layers and computing devices comprising transistors comprising channel regions comprised of strained nanoribbons or nanowires.

公开(公告)号：US20200235246A1

公开(公告)日：2020-07-23

申请号：US16647679

申请日：2018-01-10

Applicant: INTEL CORPORATION

Inventor： Abhishek A. Sharma ,  Van H. Le ,  Li Huey Tan ,  Tristan A. Tronic ,  Benjamin Chu-Kung ,  Jack T. Kavalieros ,  Tahir Ghani

IPC: H01L29/786 ,  H01L29/20 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66

Abstract: Techniques are disclosed for forming thin-film transistors (TFTs) with low contact resistance. As disclosed in the present application, the low contact resistance can be achieved by intentionally thinning one or both of the source/drain (S/D) regions of the thin-film layer of the TFT device. As the TFT layer may have an initial thickness in the range of 20-65 nm, the techniques for thinning the S/D regions of the TFT layer described herein may reduce the thickness in one or both of those S/D regions to a resulting thickness of 3-10 nm, for example. Intentionally thinning one or both of the S/D regions of the TFT layer induces more electrostatic charges inside the thinned S/D region, thereby increasing the effective dopant in that S/D region. The increase in effective dopant in the thinned S/D region helps lower the related contact resistance, thereby leading to enhanced overall device performance.

公开(公告)号：US20200212186A1

公开(公告)日：2020-07-02

申请号：US15752209

申请日：2015-09-11

Applicant: Intel Corporation

Inventor： Matthew V. Metz ,  Willy Rachmady ,  Harold W. Kennel ,  Van H. Le ,  Benjamin Chu-Kung ,  Jack T. Kavalieros ,  Gilbert Dewey

IPC: H01L29/267 ,  H01L27/092 ,  H01L29/10 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8238 ,  H01L27/11

Abstract: Embodiments related to transistors and integrated circuits having aluminum indium phosphide subfins and germanium channels, systems incorporating such transistors, and methods for forming them are discussed.

公开(公告)号：US10693008B2

公开(公告)日：2020-06-23

申请号：US14914906

申请日：2013-09-27

Applicant: Intel Corporation

Inventor： Niloy Mukherjee ,  Marko Radosavljevic ,  Jack T. Kavalieros ,  Ravi Pillarisetty ,  Niti Goel ,  Van H. Le ,  Gilbert Dewey ,  Benjamin Chu-Kung

IPC: H01L31/0256 ,  H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L21/02 ,  H01L29/423 ,  H01L29/786

Abstract: An apparatus including a semiconductor body including a channel region and junction regions disposed on opposite sides of the channel region, the semiconductor body including a first material including a first band gap; and a plurality of nanowires including a second material including a second band gap different than the first band gap, the plurality of nanowires disposed in separate planes extending through the first material so that the first material surrounds each of the plurality of nanowires; and a gate stack disposed on the channel region. A method including forming a plurality of nanowires in separate planes above a substrate, each of the plurality of nanowires including a material including a first band gap; individually forming a cladding material around each of the plurality of nanowires, the cladding material including a second band gap; coalescing the cladding material; and disposing a gate stack on the cladding material.

公开(公告)号：US20200035839A1

公开(公告)日：2020-01-30

申请号：US16043593

申请日：2018-07-24

Applicant: Intel Corporation

Inventor： Shriram Shivaraman ,  Van H. Le ,  Abhishek A. Sharma ,  Gilbert W. Dewey ,  Benjamin Chu-Kung ,  Miriam R. Reshotko ,  Jack T. Kavalieros ,  Tahir Ghani

IPC: H01L29/786 ,  H01L29/66 ,  H01L29/06 ,  H01L29/423 ,  H01L21/02 ,  H01L21/768 ,  H01L23/00

Abstract: Disclosed herein are transistor gate-channel arrangements that may be implemented in nanowire thin film transistors (TFTs) with textured semiconductors, and related methods and devices. An example transistor gate-channel arrangement may include a substrate, a channel material that includes a textured thin film semiconductor material shaped as a nanowire, a gate dielectric that at least partially wraps around the nanowire, and a gate electrode material that wraps around the gate dielectric. Implementing textured thin film semiconductor channel materials shaped as a nanowire and having a gate stack of a gate dielectric and a gate electrode material wrapping around the nanowire advantageously allows realizing gate all-around or bottom-gate transistor architectures for TFTs with textured semiconductor channel materials.

公开(公告)号：US10475888B2

公开(公告)日：2019-11-12

申请号：US15492785

申请日：2017-04-20

Applicant: Intel Corporation

Inventor： Sansaptak Dasgupta ,  Han Wui Then ,  Seung Hoon Sung ,  Sanaz K. Gardner ,  Marko Radosavljevic ,  Benjamin Chu-Kung ,  Robert S. Chau

IPC: H01L29/20 ,  H01L29/04 ,  H01L29/06 ,  H01L29/66 ,  H01L21/308 ,  H01L21/02

Abstract: An insulating layer is conformally deposited on a plurality of mesa structures in a trench on a substrate. The insulating layer fills a space outside the mesa structures. A nucleation layer is deposited on the mesa structures. A III-V material layer is deposited on the nucleation layer. The III-V material layer is laterally grown over the insulating layer.