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    Address Fault Detection In A Flash Memory System
    174.
    发明申请
    Address Fault Detection In A Flash Memory System 审中-公开

    公开(公告)号：US20190378548A1

    公开(公告)日：2019-12-12

    申请号：US16551593

    申请日：2019-08-26

    Applicant: Silicon Storage Technology, Inc.

    Inventor： Hieu Van Tran ,  Xian Liu ,  Nhan Do

    IPC: G11C7/10 ,  H01L21/28 ,  H01L27/11521 ,  G11C8/12

    Abstract: A system and method are disclosed for performing address fault detection in a flash memory system. In one embodiment, a flash memory system comprises a memory array comprising flash memory cells arranged in rows and columns, a row decoder for receiving a row address as an input, the row decoder coupled to a plurality of word lines, wherein each word line is coupled to a row of flash memory cells in the memory array, an address fault detection array comprising a column of memory cells, wherein each of the plurality of word lines is coupled to a memory cell in the column, and an analog comparator for comparing a current drawn by the column with a reference current and for indicating a fault if the current drawn by the column exceeds the reference current.

    Neural Network Classifier Using Array Of Four-Gate Non-volatile Memory Cells
    177.
    发明申请
    Neural Network Classifier Using Array Of Four-Gate Non-volatile Memory Cells 审中-公开

    公开(公告)号：US20190237142A1

    公开(公告)日：2019-08-01

    申请号：US16382034

    申请日：2019-04-11

    Applicant: Silicon Storage Technology, Inc.

    Inventor： Hieu Van Tran ,  Steven Lemke ,  Vipin Tiwari ,  Nhan Do ,  Mark Reiten

    IPC: G11C16/04 ,  H01L27/11517 ,  G06N3/04

    Abstract: A neural network device with synapses having memory cells each having a floating gate and a first gate over first and second portions of a channel region, and second and third gates over the floating gate and over the source region. First lines each electrically connect the first gates in one of the memory cell rows, second lines each electrically connect the second gates in one of the memory cell rows, third lines each electrically connect the third gates in one of the memory cell rows, fourth lines each electrically connect the source regions in one of the memory cell rows, and fifth lines each electrically connect the drain regions in one of the memory cell columns. The synapses receive a first plurality of inputs as electrical voltages on the first, second or third lines, and provide a first plurality of outputs as electrical currents on the fifth lines.

    Split gate non-volatile flash memory cell having metal gates
    180.
    发明授权
    Split gate non-volatile flash memory cell having metal gates 有权

    公开(公告)号：US10249631B2

    公开(公告)日：2019-04-02

    申请号：US15945161

    申请日：2018-04-04

    Applicant: Silicon Storage Technology, Inc.

    Inventor： Chien-Sheng Su ,  Feng Zhou ,  Jeng-Wei Yang ,  Hieu Van Tran ,  Nhan Do

    IPC: H01L29/423 ,  H01L27/11521 ,  H01L21/28 ,  H01L29/66 ,  H01L29/788 ,  H01L27/11524

    Abstract: A memory device including a silicon substrate having a planar upper surface in a memory cell area and an upwardly extending silicon fin in a logic device area. The silicon fin includes side surfaces extending up and terminating at a top surface. The logic device includes spaced apart source and drain regions with a channel region extending there between (along the top surface and the side surfaces), and a conductive logic gate disposed over the top surface and laterally adjacent to the side surfaces. The memory cell includes spaced apart source and drain regions with a second channel region extending there between, a conductive floating gate disposed over one portion of the second channel region, a conductive word line gate disposed over another portion of the second channel region, a conductive control gate disposed over the floating gate, and a conductive erase gate disposed over the source region.

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