公开(公告)号：US20230140251A1

公开(公告)日：2023-05-04

申请号：US17965282

申请日：2022-10-13

Applicant: STMicroelectronics International N.V.

Inventor： Atul DWIVEDI

IPC: G01K7/01 ,  H03M1/36 ,  H03M1/12 ,  H03M1/46 ,  G01K7/18

Abstract: A temperature sensing circuit includes a current generation circuit generating an initial current proportional to absolute temperature (Iptat), and a voltage generation circuit configured to mirror Iptat using an adjustable current source to produce a scaled current and to source the scaled current to a first terminal of a resistor to produce a reference voltage at the first terminal. A second terminal of the resistor has a voltage complementary to absolute temperature (Vctat) applied thereto. An analog-to-digital converter (ADC) has a reference input receiving the reference voltage, and a data input receiving Vctat or an externally sourced voltage. The ADC generates an output code indicative of a ratio between: a) either Vctat or the externally sourced voltage, and b) the reference voltage. A digital circuit determines a temperature readout from the output code and calibrates the reference voltage and the temperature readout determination based upon the output code.

公开(公告)号：US20230135185A1

公开(公告)日：2023-05-04

申请号：US18055245

申请日：2022-11-14

Applicant: STMICROELECTRONICS INTERNATIONAL N.V. ,  STMICROELECTRONICS S.R.L.

Inventor： Surinder Pal SINGH ,  Thomas BOESCH ,  Giuseppe DESOLI

IPC: G06N3/063 ,  G06F17/18 ,  G06N3/04 ,  G06N3/08 ,  G06F18/21

Abstract: A convolutional neural network includes a pooling unit. The pooling unit performs pooling operations between convolution layers of the convolutional neural network. The pooling unit includes hardware blocks that promote computational and area efficiency in the convolutional neural network.

公开(公告)号：US20230133385A1

公开(公告)日：2023-05-04

申请号：US17515149

申请日：2021-10-29

Applicant: STMicroelectronics Application GmbH ,  STMicroelectronics International N.V.

Inventor： Avneep Kumar Goyal ,  Thomas Szurmant

IPC: G06F21/44 ,  G06F21/31 ,  G06F21/85 ,  G06F11/36

Abstract: A system on a chip including a first-port controller for a first development port configured to receive a first development tool and a second-port controller for a second development port configured to receive a second development tool. The system on a chip further including a central controller in communication with the first-port controller, the second-port controller, and a security subsystem. The central controller being configured to manage authentication exchanges between the security subsystem and the first development tool and authentication exchanges between the security subsystem and the second development tool.

公开(公告)号：US20230110870A1

公开(公告)日：2023-04-13

申请号：US17490976

申请日：2021-09-30

Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics International N.V.

Inventor： Laura Capecchi ,  Marcella Carissimi ,  Marco Pasotti ,  Vikas Rana ,  Vivek Tyagi

IPC: G11C7/06 ,  G11C7/14

Abstract: A system and method for operating a memory cell is provided. A non-volatile memory storage device includes an array of memory cells of differential or single-ended type. In an embodiment, a regulator is coupled to a sense amplifier. The regulator is configured to generate a voltage to gate terminals of one or two transistors of the sense amplifier. In the differential type, the voltage is generated such that the first bias current and the second bias current have a current value equal to the sum of a maximum current flowing in a memory cell being in a RESET state and a fixed current. In the single-ended type, the regulated voltage is generated such that the first bias current and the second bias current have a current value equal to the sum of a fixed current and the reference current generated by the reference current source across temperature.

公开(公告)号：US20230091970A1

公开(公告)日：2023-03-23

申请号：US18052514

申请日：2022-11-03

Applicant: STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Tushar SHARMA ,  Tanmoy ROY ,  Shishir KUMAR

IPC: H01L27/11 ,  G11C5/06 ,  G11C11/412 ,  H01L27/02 ,  G11C8/16 ,  G11C11/417

Abstract: The present disclosure is directed to a circuit layout of a dual port static random-access-memory (SRAM) cell. The memory cell includes active regions in a substrate, with polysilicon gate electrodes on the active regions to define transistors of the memory cell. The eight transistor (8T) memory cell layout includes a reduced aspect ratio and non-polysilicon bit line discharge path routing by positioning an active region for the first port opposite an active region for the second port and consolidating power line nodes at a central portion of the memory cell.

公开(公告)号：US20230090782A1

公开(公告)日：2023-03-23

申请号：US17931863

申请日：2022-09-13

Applicant: STMicroelectronics International N.V.

Inventor： Anand KUMAR ,  Nitin JAIN

IPC: H03B5/36

Abstract: A low power crystal oscillator circuit having a high power part and a low power part. Oscillation is initialized using the high power part. Once the crystal is under stable oscillation, the circuit switches to the low power part and continue operation for a long duration.

公开(公告)号：US11575254B2

公开(公告)日：2023-02-07

申请号：US17095652

申请日：2020-11-11

Applicant: STMicroelectronics International N.V. ,  STMicroelectronics (Rousset) SAS

Inventor： Manoj Kumar ,  Ravinder Kumar ,  Nicolas Demange

IPC: H02H3/20 ,  H02H1/00

Abstract: An integrated circuit includes an overvoltage protection circuit. The overvoltage protection circuit detects overvoltage events at a pad of the integrated circuit. The overvoltage protection circuit generates a max voltage signal that is the greater of the voltage at the pad and a supply voltage of the integrated circuit. The overvoltage protection circuit disables a PMOS transistor coupled to the pad by supplying the max voltage signal to the gate of the PMOS transistor when an overvoltage event is present at the pad.

公开(公告)号：US11562115B2

公开(公告)日：2023-01-24

申请号：US15423284

申请日：2017-02-02

Applicant: STMICROELECTRONICS S.R.L. ,  STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Thomas Boesch ,  Giuseppe Desoli

IPC: G06N3/04 ,  G06F30/327 ,  G06N20/10 ,  G06N3/08 ,  G06F30/34 ,  G06N20/00 ,  G06N7/00 ,  G06F115/08 ,  G06N3/063 ,  G06F9/445 ,  G06F13/40 ,  G06F15/78

Abstract: Embodiments are directed towards a configurable accelerator framework device that includes a stream switch and a plurality of convolution accelerators. The stream switch has a plurality of input ports and a plurality of output ports. Each of the input ports is configurable at run time to unidirectionally pass data to any one or more of the output ports via a stream link. Each one of the plurality of convolution accelerators is configurable at run time to unidirectionally receive input data via at least two of the plurality of stream switch output ports, and each one of the plurality of convolution accelerators is further configurable at run time to unidirectionally communicate output data via an input port of the stream switch.

公开(公告)号：US20230018738A1

公开(公告)日：2023-01-19

申请号：US17812122

申请日：2022-07-12

Applicant: STMicroelectronics (Rousset) SAS ,  STMicroelectronics International N.V.

Inventor： Francesco La Rosa ,  Marco Bildgen

IPC: G11C16/04 ,  H01L27/11524 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26

Abstract: In an embodiment a noon-volatile memory device includes a memory plane including at least one memory area including an array of memory cells having two rows and N columns, wherein each memory cell comprises a state transistor having a control gate and a floating gate selectable by a vertical selection transistor buried in a substrate and including a buried selection gate, and wherein each column of memory cells includes a pair of twin memory cells, two selection transistors of the pair of twin memory cells having a common selection gate and a processor configured to store in the memory area information including a succession of N bits so that, with exception of the last bit of the succession, a current bit of the succession is stored in two memory cells located on the same row and on two adjacent columns and a current bit and the following bit are respectively stored in two twin cells.

公开(公告)号：US20230015002A1

公开(公告)日：2023-01-19

申请号：US17852677

申请日：2022-06-29

Applicant: STMicroelectronics International N.V.

Inventor： Harsh RAWAT ,  Praveen Kumar VERMA

IPC: G11C11/419 ,  G11C11/412

Abstract: A method of memory reset includes precharging bit lines of a memory array, asserting a signal at a reset node to remove the precharge voltage, and selecting write drivers associated with the bit lines associated with columns of the memory array that contain memory cells to be reset, with the assertion of the signal at the reset node also resulting in application of desired logic states to inputs of the selected write drivers to cause those selected write drivers to change a logic state of the bit lines associated with those write drivers. The method continues with asserting each word line associated with a row of the memory that contains memory cells to be reset to write desired logic states to all of the memory cells of the columns and rows of the memory to be reset during a single clock cycle, and then deasserting those word lines.