公开(公告)号：US06319798B1

公开(公告)日：2001-11-20

申请号：US09405266

申请日：1999-09-23

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L21425

CPC classification number: H01L29/6659 ,  H01L21/26506 ,  H01L21/2658 ,  H01L21/26586 ,  H01L29/1083 ,  H01L29/6653 ,  H01L29/7833

Abstract: A method for reducing lateral dopant gradient diffusion in the source/drain extension (SDE) region of a MOSFET includes forming the deep source and drain using high temperature dopant activation annealing, and then implanting a preamorphization species in an amorphized extension region that is to become the SDE region. Then, both SDE dopant and, if desired, halo dopant are implanted into the amorphized extension region and activated using relatively low temperature annealing, thereby reducing the thermal budget of the process and concomitantly reducing unwanted dopant thermal diffusion.

Abstract translation: 用于减小MOSFET的源极/漏极延伸（SDE）区域中的横向掺杂剂梯度扩散的方法包括使用高温掺杂剂激活退火形成深源极和漏极，然后在将要成为的非晶化延伸区域中植入预变质物质 SDE地区。 然后，将SDE掺杂剂和如果需要的话，卤素掺杂剂注入到非晶化延伸区域中，并使用相对低温退火进行活化，由此降低了该工艺的热预算并伴随地减少了不需要的掺杂剂热扩散。

公开(公告)号：US06312998B1

公开(公告)日：2001-11-06

申请号：US09690073

申请日：2000-10-16

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L21336

CPC classification number: H01L29/6653 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659

Abstract: For fabricating a field effect transistor, a gate structure is formed on a gate dielectric on an active device area of a semiconductor substrate. A liner layer of a non-dielectric material is formed on sidewalls of the gate dielectric, and on a drain extension area and a source extension area of the active device area of the semiconductor substrate. First spacers of dielectric material are formed on the liner layer at sidewalls of the gate structure and over the drain and source extension areas. A contact junction dopant is implanted into exposed regions of the active device area of the semiconductor substrate to form a drain contact junction and a source contact junction. The first spacers of dielectric material are etched using a first type of etching reactant that etches the first spacers but not the liner layer such that the gate dielectric is not exposed to the first type of etching reactant. The liner layer of the non-dielectric material is etched using a second type of etching reactant that etches the liner layer but not the gate structure and the gate dielectric. A first thermal anneal is performed to activate the contact junction dopant within the drain and source contact junctions. After this first thermal anneal, a drain extension junction is formed in the drain extension area and a source extension junction is formed in the source extension area by implantation of an extension junction dopant. In this manner, the drain and source extension junctions are not heated up during the first thermal anneal for activating the contact junction dopant. Thus, transient enhanced diffusion of the extension junction dopant is minimized to maintain the shallow depth of the drain and source extension junctions such that short-channel effects are minimized for the field effect transistor having scaled down dimensions.

Abstract translation: 为了制造场效应晶体管，在半导体衬底的有源器件区域上的栅极电介质上形成栅极结构。 在栅极电介质的侧壁上以及在半导体衬底的有源器件区域的漏极延伸区域和源极延伸区域上形成非电介质材料的衬里层。 介电材料的第一间隔物在栅极结构的侧壁和漏极和源极延伸区域的衬里层上形成。 将接触结掺杂剂注入到半导体衬底的有源器件区域的暴露区域中以形成漏极接触结和源极接触结。 使用蚀刻第一间隔物而不是衬里层的第一类型蚀刻反应物蚀刻介电材料的第一间隔物，使得栅极电介质不暴露于第一类型的蚀刻反应物。 使用蚀刻衬里层而不是栅极结构和栅极电介质的第二类型蚀刻反应物来蚀刻非介电材料的衬里层。 执行第一热退火以激活漏极和源极接触接合处的接触结掺杂剂。 在该第一热退火之后，在漏极延伸区域中形成漏极延伸结，并且通过注入延伸结掺杂剂在源极延伸区域中形成源极延伸结。 以这种方式，在用于激活接触结掺杂剂的第一热退火期间，漏极和源极延伸接头不被加热。 因此，延伸结掺杂剂的瞬时增强的扩散被最小化以保持漏极和源极延伸结的浅深度，使得对具有缩小尺寸的场效应晶体管的短沟道效应最小化。

公开(公告)号：US06291302B1

公开(公告)日：2001-09-18

申请号：US09483528

申请日：2000-01-14

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L21336

CPC classification number: H01L21/268 ,  H01L21/26513 ,  H01L21/324 ,  H01L29/6659

Abstract: A method of providing a field effect transistor includes depositing a layer of a laser-reflective material on a substrate which has an active region and an inactive region; selectively removing portions of the deposited layer disposed over the active region; exposing laser energy to activate dopants in the active region; and stripping the deposited layer.

Abstract translation: 提供场效应晶体管的方法包括在具有有源区和非活性区的衬底上沉积激光反射材料层; 选择性地去除设置在有源区上的沉积层的部分; 暴露激光能量以激活有源区中的掺杂剂; 并剥离沉积层。

公开(公告)号：US06284630B1

公开(公告)日：2001-09-04

申请号：US09421304

申请日：1999-10-20

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L2104

CPC classification number: H01L29/6659 ,  H01L21/26506 ,  H01L21/2652 ,  H01L21/26586 ,  H01L21/268 ,  H01L29/665

Abstract: Drain and source extensions that are abrupt and shallow and that have high concentration of dopant are fabricated for a field effect transistor, using a laser thermal process. A drain amorphous region is formed by implanting a neutral species into a drain region of the field effect transistor at an angle directed toward a gate of the field effect transistor such that the drain amorphous region is a trapezoidal shape that extends to be sufficiently under the gate of the field effect transistor. A source amorphous region is formed by implanting the neutral species into a source region of the field effect transistor at an angle directed toward the gate of the field effect transistor such that the source amorphous region is a trapezoidal shape that extends to be sufficiently under the gate of the field effect transistor. A drain and source dopant is implanted into the drain and source amorphous regions at an angle directed toward the gate of the field effect transistor. A laser beam is then applied to the drain and source amorphous regions such that the drain and source dopant is activated within the drain and source amorphous regions in a laser thermal process. The drain and source extensions are formed by the activation of the drain and source dopant in the drain and source amorphous regions respectively during the laser thermal process. The trapezoidal shape of the drain and source extensions minimizes the series resistance and the leakage current in the field effect transistor having scaled down dimensions.

Abstract translation: 使用激光热处理为场效应晶体管制造突变和浅的并且具有高浓度掺杂剂的漏极和源极延伸。 通过以场效应晶体管的栅极朝向场效应晶体管的栅极注入中性物质到场效应晶体管的漏极区域中形成漏极非晶区域，使得漏极非晶区域是梯形形状，其延伸到栅极下方 的场效应晶体管。 源极非晶区域是通过将中性物质注入场效应晶体管的源极区域而形成的，其角度指向场效应晶体管的栅极，使得源极非晶区域是梯形形状，其延伸足以在栅极 的场效应晶体管。 漏极和源极掺杂剂以指向场效应晶体管的栅极的角度注入到漏极和源极非晶区域中。 然后将激光束施加到漏极和源极非晶区域，使得漏极和源极掺杂剂在激光热处理中在漏极和源非晶区域内被激活。 漏极和源极延伸部分分别在激光热处理期间激活漏极和源非晶区域中的漏极和源极掺杂物。 漏极和源极延伸的梯形形状使具有缩小尺寸的场效应晶体管中的串联电阻和漏电流最小化。

公开(公告)号：US06271095B1

公开(公告)日：2001-08-07

申请号：US09255546

申请日：1999-02-22

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L21336

CPC classification number: H01L29/66492 ,  H01L29/665

Abstract: A method of fabricating an integrated circuit with locally confined deep pocket regions utilizes a dummy or sacrificial gate spacer. Dopants are provided through the openings associated with sacrificial spacers to form the pocket regions. The dopants are provided after silicidation. The openings can be filled with spacers. The process can be utilized for P-channel or N-channel metal oxide field semiconductor effect transistors (MOSFETS).

Abstract translation: 制造具有局部密封深口袋区域的集成电路的方法利用虚拟或牺牲栅极间隔物。 通过与牺牲间隔物相关联的开口提供掺杂剂以形成袋区域。 在硅化后提供掺杂剂。 开口可以填充间隔件。 该过程可用于P沟道或N沟道金属氧化物半导体效应晶体管（MOSFET）。

公开(公告)号：US06248637B1

公开(公告)日：2001-06-19

申请号：US09405831

申请日：1999-09-24

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L21336

CPC classification number: H01L21/28202 ,  H01L21/28123 ,  H01L29/41783 ,  H01L29/511 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66492 ,  H01L29/665

Abstract: An ultra-large-scale integrated (ULSI) circuit includes MOSFETs on a substrate. The MOSFETs include elevated source and drain regions. The elevated source and drain regions are adjacent ultra-shallow source and drain regions. Dopants in the ultra-shallow source and drain regions are activated in a low-temperature rapid thermal anneal process.

Abstract translation: 超大规模集成（ULSI）电路在衬底上包括MOSFET。 MOSFET包括升高的源极和漏极区域。 升高的源极和漏极区域是相邻的超浅源极和漏极区域。 在超浅源极和漏极区域中的掺杂剂在低温快速热退火工艺中被激活。

公开(公告)号：US06228721B1

公开(公告)日：2001-05-08

申请号：US09602666

申请日：2000-06-26

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L218234

CPC classification number: H01L21/823462 ,  Y10S438/981

Abstract: For fabricating a metal oxide structure on a semiconductor substrate, an active device area surrounded by at least one STI (shallow trench isolation) structure is formed in the semiconductor substrate. A layer of metal is deposited on the semiconductor substrate, and the layer of metal contacts the active device area of the semiconductor substrate. A layer of oxygen blocking material is deposited on the layer of metal. An opening is etched through the layer of oxygen blocking material to expose an area of the layer of metal on top of the active device area. A thermal oxidation process is performed to form a metal oxide structure from reaction of oxygen with the area of the layer of metal that is exposed. A thickness of the metal oxide structure is determined by a thickness of the layer of metal, and the layer of oxygen blocking material prevents contact of oxygen with the layer of metal such that the metal oxide structure is formed localized at the area where the layer of metal is exposed. In this manner, the metal oxide structure is formed by localized thermal oxidation of the layer of metal such that a deposition or sputtering process or an etching process is not necessary for formation of the metal oxide structure. In addition, the thickness of the metal oxide structure is determined by controlling the thickness of the layer of metal used for forming the metal oxide structure. Furthermore, these steps may be repeated for another layer of metal having a different thickness for forming a plurality of metal oxide structures having different thicknesses to provide gate dielectrics of MOSFETs (metal oxide semiconductor field effect transistors) having different threshold voltages on the same semiconductor substrate.

Abstract translation: 为了在半导体衬底上制造金属氧化物结构，在半导体衬底中形成由至少一个STI（浅沟槽隔离）结构包围的有源器件区域。 一层金属沉积在半导体衬底上，金属层与半导体衬底的有源器件区接触。 一层氧阻塞材料沉积在金属层上。 通过氧阻挡材料层蚀刻开口以暴露活性器件区域顶部的金属层的区域。 进行热氧化处理以形成金属氧化物结构，从氧与暴露的金属层的面积的反应。 金属氧化物结构的厚度由金属层的厚度确定，并且氧阻挡材料层防止氧与金属层的接触，使得金属氧化物结构形成在区域 金属被暴露。 以这种方式，通过金属层的局部热氧化形成金属氧化物结构，使得形成金属氧化物结构不需要沉积或溅射工艺或蚀刻工艺。 此外，通过控制用于形成金属氧化物结构的金属层的厚度来确定金属氧化物结构的厚度。 此外，可以对具有不同厚度的另一层金属重复这些步骤，以形成具有不同厚度的多个金属氧化物结构，以在同一半导体衬底上提供具有不同阈值电压的MOSFET（金属氧化物半导体场效应晶体管）的栅极电介质 。

公开(公告)号：US06225176B1

公开(公告)日：2001-05-01

申请号：US09255203

申请日：1999-02-22

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L21336

CPC classification number: H01L29/6659 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/268 ,  H01L29/665 ,  H01L29/6656

Abstract: A method of fabricating an integrated circuit with a step source/drain junction utilizes a triple amorphization technique. The technique creates a shallow amorphous region, an intermediate region and a deep amorphous region. The doped amorphous regions can be laser-annealed to form step-like source/drain junctions and their extensions. The process can be utilized for P-channel or N-channel metal-oxide-semiconductor field-effect transistors (MOSFETs).

Abstract translation: 制造具有阶跃源极/漏极结的集成电路的方法利用三次非晶化技术。 该技术产生浅的非晶区域，中间区域和深非晶区域。 掺杂的非晶区域可以被激光退火以形成阶梯状源极/漏极结及其延伸。 该过程可用于P沟道或N沟道金属氧化物半导体场效应晶体管（MOSFET）。

公开(公告)号：US6165849A

公开(公告)日：2000-12-26

申请号：US205616

申请日：1998-12-04

Applicant: Judy X. An ,  Bin Yu

Inventor： Judy X. An ,  Bin Yu

IPC: H01L21/8234 ,  H01L21/336

CPC classification number: H01L21/823462

Abstract: A semiconductor device is formed having a low voltage transistor in a logic core portion and a high voltage transistor in an input/output portion. The low voltage transistor is formed by ion implanting nitrogen into the surface and forming a gate oxide layer on the nitrogen implanted surface portion of the semiconductor substrate in the logic core region. The implanted nitrogen retards the growth of the gate oxide layer in the nitrogen implanted area, thereby enabling formation of gate oxide layers having different thicknesses.

Abstract translation: 半导体器件形成为具有逻辑芯部分中的低电压晶体管和输入/输出部分中的高压晶体管。 低压晶体管通过将氮离子注入到表面中并在逻辑核心区域中的半导体衬底的氮注入表面部分上形成栅极氧化物层而形成。 植入的氮阻止氮注入区域中的栅极氧化物层的生长，从而能够形成具有不同厚度的栅极氧化物层。

公开(公告)号：US6066533A

公开(公告)日：2000-05-23

申请号：US163290

申请日：1998-09-29

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L21/8234

CPC classification number: H01L21/82345

Abstract: A method for making a ULSI MOSFET includes depositing a high-k gate insulator on a silicon substrate and then depositing a field oxide layer over the gate insulator. The field oxide layer is masked with photoresist and the photoresist patterned to establish first gate windows, and the oxide below the windows is then etched away to establish first gate voids in the oxide. The first gate voids are filled with a first metallic gate electrode material that is suitable for establishing a gate electrode of, e.g., an N-channel MOSFET. Second gate voids are similarly made in the oxide and filled with a second gate electrode material that is suitable for establishing a gate electrode of, e.g., an P-channel MOSFET or another N-channel MOSFET having a different threshold voltage than the first MOSFET. With this structure, plural threshold design voltages are supported in a single ULSI chip that uses high-k gate insulator technology.

Abstract translation: 制造ULSI MOSFET的方法包括在硅衬底上沉积高k栅极绝缘体，然后在栅极绝缘体上沉积场氧​​化物层。 用光致抗蚀剂掩蔽场氧化物层，并且将光致抗蚀剂图案化以建立第一栅极窗口，然后蚀刻掉窗口下面的氧化物以在氧化物中建立第一栅极空隙。 第一栅极空隙填充有适于建立例如N沟道MOSFET的栅电极的第一金属栅电极材料。 第二栅极空隙类似地在氧化物中制成并且填充有适于建立例如P沟道MOSFET或具有不同于第一MOSFET的阈值电压的另一N沟道MOSFET的栅电极的第二栅电极材料。 利用这种结构，在使用高k栅极绝缘体技术的单个ULSI芯片中支持多个阈值设计电压。