公开(公告)号：US11469230B2

公开(公告)日：2022-10-11

申请号：US17188083

申请日：2021-03-01

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Haitao Liu ,  Litao Yang

IPC: H01L27/108 ,  H01L27/11507

Abstract: Systems, methods and apparatus are provided for an array of vertically stacked memory cells. The vertically stacked memory cells have horizontally oriented access devices having a first source/drain region, a channel region, and a second source drain and storage nodes that are vertically separated from the access devices.

公开(公告)号：US20220278103A1

公开(公告)日：2022-09-01

申请号：US17745298

申请日：2022-05-16

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Karthik Sarpatwari ,  Haitao Liu ,  Durai Vishak Nirmal Ramaswamy

IPC: H01L27/105 ,  H01L27/12 ,  H01L29/788 ,  H01L29/24 ,  H01L29/786

Abstract: Some embodiments include apparatuses and methods using a substrate, a pillar having a length perpendicular to the substrate, a first conductive plate, a second conductive plate, a memory cell located between the first and second conductive plates and electrically separated from the first and second conductive plates, and a conductive connection. The first conductive plate is located in a first level of the apparatus and being separated from the pillar by a first dielectric located in the first level. The second conductive plate is located in a second level of the apparatus and being separated from the pillar by a second dielectric located in the second level. The memory cell includes a first semiconductor material located in a third level of the apparatus between the first and second levels and contacting the pillar and the conductive connection, and a second semiconductor material located in a fourth level of the apparatus between the first and second levels and contacting the pillar.

公开(公告)号：US11430895B2

公开(公告)日：2022-08-30

申请号：US16891462

申请日：2020-06-03

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Guangyu Huang ,  Haitao Liu ,  Akira Goda

IPC: H01L29/786 ,  H01L27/11529 ,  H01L27/11573 ,  H01L29/66

Abstract: A transistor comprises a lower contact structure, a channel structure, a dielectric fill structure, and an upper contact structure. The lower contact structure comprises a first oxide semiconductive material. The channel structure contacts the lower contact structure and comprises a second oxide semiconductive material having a smaller atomic concentration of one or more metals than the first oxide semiconductive material. The dielectric fill structure contacts an inner side surface of the channel structure and has a recessed upper surface relative to the channel structure. The upper contact structure comprises a third oxide semiconductive material having a greater atomic concentration of the one or more metals than the channel structure. The upper contact structure comprises a first portion contacting the upper surface of the dielectric fill structure and the inner side surface of the channel structure, and a second portion contacting the upper surface of the channel structure.

公开(公告)号：US20220223605A1

公开(公告)日：2022-07-14

申请号：US17712674

申请日：2022-04-04

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Karthik Sarpatwari ,  Durai Vishak Nirmal Ramaswamy ,  Haitao Liu

IPC: H01L27/108

Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a memory cell and first, second, and third data lines located over a substrate. The memory cell includes a first transistor and a second transistor. The first transistor includes a charge storage structure located on a first level of the apparatus, and a first channel region electrically separated from the charge storage structure. The second transistor includes a second channel region located on a second level of the apparatus and electrically coupled to the charge storage structure. The first and second data lines are located on a third level of the apparatus and electrically coupled to the first channel region. The first level is between the substrate and the third level. The third data line is electrically coupled to the second channel region and electrically separated from the first channel region.

公开(公告)号：US11373913B2

公开(公告)日：2022-06-28

申请号：US16558928

申请日：2019-09-03

Applicant: Micron Technology, Inc.

Inventor： Deepak Chandra Pandey ,  Haitao Liu ,  Kamal M. Karda

IPC: H01L29/66 ,  H01L21/8238 ,  H01L21/8234 ,  H01L29/08 ,  H01L29/10 ,  H01L29/78 ,  H01L27/1159 ,  H01L27/11507 ,  H01L23/528 ,  H01L29/786 ,  H01L29/792 ,  H01L27/24 ,  H01L21/8239 ,  H01L27/108 ,  H01L21/768 ,  H01L21/311

Abstract: An array of vertical transistors comprises spaced pillars individually comprising a channel region of individual vertical transistors. A horizontally-elongated conductor line directly electrically couples together individual of the channel regions of the pillars of a plurality of the vertical transistors. An upper source/drain region is above the individual channel regions of the pillars, a lower source/drain region is below the individual channel regions of the pillars, and a conductive gate line is operatively aside the individual channel regions of the pillars and that interconnects multiple of the vertical transistors. Methods are disclosed.

公开(公告)号：US11302703B2

公开(公告)日：2022-04-12

申请号：US16803948

申请日：2020-02-27

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Chandra Mouli ,  Srinivas Pulugurtha ,  Rajesh N. Gupta

IPC: H01L27/112 ,  H01L27/108 ,  H01L49/02 ,  G11C11/4074 ,  H01L29/08 ,  H01L27/11556 ,  H01L21/8234 ,  H01L21/84 ,  H01L21/8238 ,  H01L27/11582 ,  G11C11/408 ,  H01L27/07 ,  H01L27/11553 ,  H01L29/92 ,  G11C5/14 ,  G11C5/06

Abstract: Some embodiments include a memory cell with two transistors and one capacitor. The transistors are a first transistor and a second transistor. The capacitor has a first node coupled with a source/drain region of the first transistor, and has a second node coupled with a source/drain region of the second transistor. The memory cell has a first body region adjacent the source/drain region of the first transistor, and has a second body region adjacent the source/drain region of the second transistor. A first body connection line couples the first body region of the memory cell to a first reference voltage. A second body connection line couples the second body region of the memory cell to a second reference voltage. The first and second reference voltages may be the same as one another, or may be different from one another.

公开(公告)号：US20210375893A1

公开(公告)日：2021-12-02

申请号：US17445134

申请日：2021-08-16

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Akira Goda ,  Sanh D. Tang ,  Gurtej S. Sandhu ,  Litao Yang ,  Haitao Liu

IPC: H01L27/11524 ,  H01L27/1157 ,  H01L29/24 ,  H01L29/786 ,  H01L23/522 ,  H01L27/11556 ,  H01L27/11582 ,  H01L23/528

Abstract: A transistor comprises a 2D material structure and a gate structure. The 2D material structure conformally extends on and between surfaces of dielectric fin structures extending in parallel in a first horizontal direction, and comprises a source region, a drain region, and a channel region positioned between the source region and the drain region in the first horizontal direction. The gate structure overlies the channel region of the 2D material structure and extends in a second horizontal direction orthogonal to the first horizontal direction. The gate structure is within horizontal boundaries of the channel region of the 2D material structure in the first horizontal direction. Microelectronic devices, memory devices, and electronic systems are also described.

公开(公告)号：US11177265B2

公开(公告)日：2021-11-16

申请号：US16862122

申请日：2020-04-29

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Si-Woo Lee ,  Haitao Liu ,  Deepak Chandra Pandey

IPC: H01L27/108 ,  H01L29/10 ,  H01L29/49 ,  H01L29/167

Abstract: Some embodiments include an integrated assembly having an active-region-pillar extending upwardly from a base. The active-region-pillar includes a digit-line-contact-region between a first storage-element-contact-region and a second storage-element-contact-region. A threshold-voltage-inducing-structure is adjacent a lower portion of the active-region-pillar. A first channel region includes a first portion of the active-region-pillar between the digit-line-contact-region and the first storage-element-contact-region. A second channel region includes a second portion of the active-region-pillar between the digit-line-contact-region and the second storage-element-contact-region. A first wordline is adjacent the first portion of the active-region-pillar. A second wordline is adjacent the second portion of the active-region-pillar. A digit-line is coupled with the digit-line-contact-region. First and second storage-elements are coupled with the first and second storage-element-contact-regions. A voltage source is coupled with the threshold-voltage-inducing-structure to electrostatically induce a desired threshold voltage along the first and second channel regions.

公开(公告)号：US11171206B2

公开(公告)日：2021-11-09

申请号：US16509093

申请日：2019-07-11

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Haitao Liu ,  Si-Woo Lee ,  Fatma Arzum Simsek-Ege ,  Deepak Chandra Pandey ,  Chandra V. Mouli ,  John A. Smythe, III

IPC: H01L29/06 ,  H01L27/108 ,  H01L21/762

Abstract: An example apparatus includes a first source/drain region and a second source/drain region formed in a substrate to form an active area of the apparatus. The first source/drain region and the second source/drain region are separated by a channel. The apparatus includes a gate opposing the channel. A sense line is coupled to the first source/drain region and a storage node is coupled to the second source/drain region. An isolation trench is adjacent to the active area. The trench includes a dielectric material with a conductive bias opposing the conductive bias of the channel in the active area.

公开(公告)号：US11139396B2

公开(公告)日：2021-10-05

申请号：US16596090

申请日：2019-10-08

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Durai Vishak Nirmal Ramaswamy ,  Haitao Liu

IPC: H01L29/78 ,  H01L29/786 ,  H01L21/02 ,  H01L29/66

Abstract: A device comprises a first conductive line and a vertical transistor over the first conductive line. The vertical transistor comprises a gate electrode, a gate dielectric material overlying sides of the gate electrode, and a channel region on sides of the gate dielectric material, the gate dielectric material located between the channel region and the gate electrode. The device further comprises a second conductive line overlying a conductive contact of the at least one vertical transistor. Related devices and methods of forming the devices are also disclosed.