公开(公告)号：US5396108A

公开(公告)日：1995-03-07

申请号：US129257

申请日：1993-09-30

申请人： David C. McClure

发明人： David C. McClure

IPC分类号： G11C11/417 ,  G11C11/407 ,  G11C11/409 ,  H03K3/356 ,  H03K17/687 ,  H03K19/0175 ,  H03K19/094 ,  H03K17/296 ,  H03K17/795

CPC分类号： H03K19/09429

摘要： A latch output driver including an output driver circuit having a pull-up transistor and a pull-down transistor connected in series, wherein the pull-up transistor has a drain connected to an upper power supply voltage and a source connected to a drain of the pull-down transistor and the pull-down transistor has a source connected to a lower power supply voltage. The latch controlled output driver also includes a first latch circuit having an output connected to the gate of the pull-up transistor and a second latch circuit having an output connected to the gate of the pull-down transistor. A control circuit is connected to the first and second latches, wherein the control circuit may selectively disable and enable the latch controlled output driver in response to a control signal. A driver output is connected between the pull-up and pull-down transistors, wherein the output driver is in an open state when the latch controlled output driver is disabled by the control circuit. A data circuit is connected to the first and second latch circuits, wherein the data circuit stores the state of the first and second latches present when the latch controlled output driver is enabled and restores the state of the first and second latches when the latch controlled output driver is enabled after being disabled.

摘要翻译： 一种锁存器输出驱动器，包括具有串联连接的上拉晶体管和下拉晶体管的输出驱动器电路，其中上拉晶体管具有连接到上电源电压的漏极和连接到上电源电压的漏极的源极 下拉晶体管和下拉晶体管具有连接到较低电源电压的源极。 锁存控制输出驱动器还包括具有连接到上拉晶体管的栅极的输出的第一锁存电路和具有连接到下拉晶体管的栅极的输出的第二锁存电路。 控制电路连接到第一和第二锁存器，其中控制电路可以响应于控制信号而选择性地禁用和使能锁存控制的输出驱动器。 驱动器输出连接在上拉和下拉晶体管之间，其中当锁存控制的输出驱动器被控制电路禁用时，输出驱动器处于打开状态。 数据电路连接到第一和第二锁存电路，其中当锁存控制的输出驱动器被使能时，数据电路存储存在的第一和第二锁存器的状态，并且当锁存器控制输出时恢复第一和第二锁存器的状态 驱动程序在禁用后启用。

公开(公告)号：US5386377A

公开(公告)日：1995-01-31

申请号：US122804

申请日：1993-09-16

申请人： David C. McClure

发明人： David C. McClure

IPC分类号： G06F7/50 ,  G06F7/508

CPC分类号： G06F7/508

摘要： Therefore, according to the present invention, borrow look ahead circuitry suitable for use in a FIFO memory allows the difference between two values to be quickly generated and this difference compared to a third value. A borrow look ahead element generates a plurality of borrow signals which are supplied to CORRESPONDING full subtractors of a subtractor section in a parallel fashion. This parallel propagation reduces gates delays between the subtractors, resulting in faster operation. Thus, the time required to supply the difference to a comparator is minimized. Adding additional levels to the borrow look ahead element further increases the speed of the borrow look ahead circuitry.

摘要翻译： 因此，根据本发明，适用于FIFO存储器的借用前瞻电路允许快速产生两个值之间的差异，并且该差异与第三值相比较。 借用前瞻元素产生多个借位信号，其以并行方式提供给减法器部分的CORRESPONDING完全减法器。 这种并行传播减少了减法器之间的门延迟，导致更快的操作。 因此，将差异提供给比较器所需的时间被最小化。 向借用前瞻元素添加额外的级别进一步增加了借用前瞻电路的速度。

公开(公告)号：US5381126A

公开(公告)日：1995-01-10

申请号：US923855

申请日：1992-07-31

申请人： David C. McClure

发明人： David C. McClure

IPC分类号： G06F5/06 ,  G05B1/00

CPC分类号： G06F5/06

摘要： Difference flag logic suitable for use in a FIFO memory is modified to quickly generate FIFO flag status through the use of programmable, resettable counters which eliminate the need for subtractor circuitry. A comparator is used to compare a value from a read counter with a value from a write counter. The subtractor function is replaced by offsetting the read count from the write count by a value equal to the desired FIFO flag value. Offset of the read count from the write count is accomplished by utilizing counters which provide programmable resettability. Use of programmable, resettable counters allows FIFO flag values to be chosen and implemented very easily. For instance, it is possible for a user to change from an almost full FIFO flag to a half full FIFO flag without changing any hardware at all. The counters are simply programmed and reset accordingly.

摘要翻译： 适用于FIFO存储器的差分标志逻辑被修改为通过使用可编程的可复位计数器来快速生成FIFO标志状态，从而消除对减法器电路的需要。 比较器用于将来自读计数器的值与来自写计数器的值进行比较。 通过将写入计数的读取计数与期望的FIFO标志值相等的值来抵消减法器功能。 通过使用提供可编程可重定位性的计数器来实现从写入计数读取计数的偏移。 使用可编程的可复位计数器可以非常容易地选择和实现FIFO标志值。 例如，用户可以从几乎完全的FIFO标志变为半完整的FIFO标志，而不改变任何硬件。 计数器被简单地编程并相应地复位。

公开(公告)号：US5377150A

公开(公告)日：1994-12-27

申请号：US99947

申请日：1993-07-30

申请人： David C. McClure

发明人： David C. McClure

IPC分类号： G11C7/06 ,  G11C7/02

CPC分类号： G11C7/062 ,  G11C7/065

摘要： A memory system that includes a memory array having at least two pairs of data lines, first and second data lines that correspond to columns in the memory array. The memory array also includes two disabling sense amplifier circuits, a first disabling sense amplifier circuit connected to the first data lines and a disabling sense amplifier circuit connected to the second data lines, wherein the disabling sense amplifier circuits produce output signals and may be enabled and disabled. A selection signal is provided for selectively enabling and disabling the disabling sense amplifier circuits, wherein one pair of data lines may be selected. An amplification circuit connected to the disabling sense amplifier circuits provides for amplifying the output signals from the disabling sense amplifier circuits.

摘要翻译： 一种存储器系统，其包括具有至少两对数据线的存储器阵列，对应于存储器阵列中的列的第一和第二数据线。 存储器阵列还包括两个禁用读出放大器电路，连接到第一数据线的第一禁用读出放大器电路和连接到第二数据线的禁用读出放大器电路，其中禁用读出放大器电路产生输出信号并且可被使能， 残疾人士 提供选择信号用于选择性地启用和禁用禁用读出放大器电路，其中可以选择一对数据线。 连接到禁用读出放大器电路的放大电路提供放大来自禁用读出放大器电路的输出信号。

公开(公告)号：US5357236A

公开(公告)日：1994-10-18

申请号：US890919

申请日：1992-05-29

申请人： David C. McClure

发明人： David C. McClure

IPC分类号： G11C7/00 ,  G06F5/06 ,  G06F5/10 ,  G06F5/12 ,  G06F5/14 ,  G06F7/02

CPC分类号： G06F5/14

摘要： Difference flag logic suitable for use in a FIFO memory is modified to quickly generate FIFO flag status without the use of subtractor circuitry. Bit comparators, which determine if a first bit is less than, equal to, or greater than a second bit, of a magnitude comparator are divided into groups which generate compare output signals in parallel to one another, thereby reducing total magnitude comparator delay and resulting in faster operation. These compare output signals are the inputs of a control element which determines which compare output signal is allowed to pass through as the final compare output signal. The subtractor function is replaced by offsetting the read count from the write count by a value equal to the desired FIFO flag value. In addition, control of selected bits, such as the most significant bits (MSBs), of the numbers is included and may be used as necessary to avoid a wrap-around condition.

摘要翻译： 适用于FIFO存储器的差分标志逻辑被修改为在不使用减法器电路的情况下快速生成FIFO标志状态。 确定幅度比较器的第一位是否小于等于或大于第二位的比特比较器被划分成彼此并联的生成比较输出信号的组，从而减少总幅度比较器的延迟并导致 在更快的操作。 这些比较输出信号是控制元件的输入，其确定允许哪个比较输出信号作为最终比较输出信号通过。 通过将写入计数的读取计数与期望的FIFO标志值相等的值来抵消减法器功能。 此外，包括数字的选择位（诸如最高有效位（MSB））的控制，并且可以根据需要使用以避免环绕条件。

公开(公告)号：US5349243A

公开(公告)日：1994-09-20

申请号：US85760

申请日：1993-06-30

申请人： David C. McClure

发明人： David C. McClure

IPC分类号： G11C11/417 ,  G11C11/409 ,  G11C16/06 ,  G11C17/00 ,  H03K19/00 ,  H03K19/0175 ,  H03K3/284 ,  H03K3/01

CPC分类号： H03K19/0013

摘要： An output driver includes a pull-up and a pull-down transistor in series between an upper and a lower power supply voltage. Each transistor is controlled by a latch connected to its gate. Control transistors are cross-coupled between inputs to the latches and a power supply voltage to force at least one of the latches to be in a known state. This prevents both of the transistors from turning on simultaneously.

摘要翻译： 输出驱动器包括上下电源电压串联的上拉和下拉晶体管。 每个晶体管由连接到其栅极的锁存器控制。 控制晶体管在锁存器的输入之间交叉耦合，并且电源电压被迫使至少一个锁存器处于已知状态。 这样可以防止两个晶体管同时导通。

公开(公告)号：US5341336A

公开(公告)日：1994-08-23

申请号：US56376

申请日：1993-04-30

申请人： David C. McClure

发明人： David C. McClure

IPC分类号： G01R31/30 ,  G11C11/413 ,  G11C29/00 ,  G11C29/02 ,  G11C29/06 ,  G11C7/00

CPC分类号： G11C29/02

摘要： A method for stress testing decoders and other periphery circuits used with a memory array. An address buffer simultaneously sets the inputs of a plurality of decoders to a first common voltage level, so that a plurality of rows and/or columns within the memory array are selected for a predetermined period of time. A stress voltage is then applied to the integrated circuit to stress test the gate oxides within the decoders and other periphery circuits. The inputs of the plurality of decoders are then simultaneously set to a second common voltage level, so that the plurality of rows and/or columns within the memory array are deselected. Finally, a stress voltage is applied to the integrated circuit to stress test the gate oxides within the decoders and other periphery circuits.

摘要翻译： 一种用于对存储器阵列使用的解码器和其它外围电路进行压力测试的方法。 地址缓冲器同时将多个解码器的输入设置为第一公共电压电平，使得在预定时间段内选择存储器阵列内的多个行和/或列。 然后将应力电压施加到集成电路以对解码器和其它外围电路中的栅极氧化物进行测试。 然后，多个解码器的输入被同时设置为第二公共电压电平，使得存储器阵列内的多个行和/或列被取消选择。 最后，对集成电路施加应力电压，对解码器和其他外围电路中的栅极氧化物进行测试。

公开(公告)号：US5339277A

公开(公告)日：1994-08-16

申请号：US56078

申请日：1993-04-30

申请人： David C. McClure

发明人： David C. McClure

IPC分类号： G11C11/413 ,  G11C8/06 ,  G11C8/12 ,  G11C29/00 ,  G11C29/34 ,  G11C8/00

CPC分类号： G11C8/06 ,  G11C29/34 ,  G11C8/12

摘要： An address buffer which allows for the simultaneous selection and/or deselection of a plurality of rows and/or columns within a memory array. A first and a second circuit generate a true and a complementary signal, respectively, during normal operations of the integrated circuit. When desired, the first and second circuits may be used to generate two signals of the same voltage level. The two signals of the same voltage level may then be used by an address decoder to simultaneously select and/or deselect a plurality of rows and/or columns within a memory array.

摘要翻译： 一种地址缓冲器，其允许在存储器阵列内同时选择和/或取消选择多个行和/或列。 在集成电路的正常操作期间，第一和第二电路分别产生真实的和互补的信号。 当需要时，第一和第二电路可用于产生相同电压电平的两个信号。 然后可以由地址解码器使用相同电压电平的两个信号来同时选择和/或取消选择存储器阵列内的多个行和/或列。

公开(公告)号：US5258952A

公开(公告)日：1993-11-02

申请号：US627236

申请日：1990-12-14

申请人： Thomas A. Coker ,  David C. McClure

发明人： Thomas A. Coker ,  David C. McClure

IPC分类号： G11C11/41 ,  G11C7/22 ,  G11C8/18 ,  G11C7/00

CPC分类号： G11C8/18 ,  G11C7/22

摘要： A read/write memory having timed-out control of certain of its peripheral circuitry is disclosed. The control circuit for controlling the time at which time-out is to occur includes two delay stages of different lengths. The shorter delay stage is used to define the time-out in a read operation, and the longer delay stage is used to define the time-out in a write operation, since a read operation can generally be accomplished sooner than a write operation. Enabling of the periphery is controlled by an address transition detection circuit, and by a data transition detection circuit. The circuit includes a short path by which enabling of the periphery is performed responsive to a data transition in the absence of an address transition, in order to perform a late write operation.

公开(公告)号：US5257229A

公开(公告)日：1993-10-26

申请号：US830314

申请日：1992-01-31

申请人： David C. McClure ,  Narasimhan Iyengar

发明人： David C. McClure ,  Narasimhan Iyengar

IPC分类号： G11C11/401 ,  G11C29/00 ,  G11C29/04 ,  G11C7/00

CPC分类号： G11C29/808 ,  G11C29/846 ,  G11C29/78

摘要： An integrated circuit memory is disclosed which has its primary memory array arranged into blocks and which has redundant columns, each of which can replace a column in any one of the blocks. The redundant columns are selected by way of a redundant column decoder, associated with each column. A plurality of redundant sense amplifiers are each associated with selected redundant columns. Each of the redundant column decoders includes a set of fuses for storing the column address responsive to which its associated redundant column is to be selected. The coupling of each redundant sense amplifier is controlled by a redundant multiplexer associated with each of the input/output terminals. Each redundant multiplexer receives the redundant column select signals from each redundant column decoder corresponding thereto, and includes fuses which indicate if its input/output terminal is to be placed in communication with its associated sense amplifier upon selection of a redundant column.

摘要翻译： 公开了一种集成电路存储器，其具有排列成块的主存储器阵列，并且具有冗余列，每个列可替代任何一个块中的列。 通过冗余列解码器选择冗余列，与列相关联。 多个冗余感测放大器各自与所选择的冗余列相关联。 冗余列解码器中的每一个包括一组保险丝，用于存储响应于其相关联的冗余列被选择的列地址。 每个冗余读出放大器的耦合由与每个输入/输出端子相关联的冗余多路复用器控制。 每个冗余多路复用器从对应于其的每个冗余列解码器接收冗余列选择信号，并且包括指示其选择冗余列时是否将其输入/输出端子与其相关联的读出放大器通信的熔丝。