公开(公告)号：US11568919B2

公开(公告)日：2023-01-31

申请号：US17334170

申请日：2021-05-28

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Suresh Rajan ,  Scott C. Best

IPC: G11C11/408 ,  G11C5/04 ,  G11C11/4093 ,  G06F12/06 ,  G06F13/16 ,  G11C7/10 ,  G11C7/22 ,  G11C11/4076

Abstract: The embodiments described herein describe technologies for using the memory modules in different modes of operation, such as in a standard multi-drop mode or as in a dynamic point-to-point (DPP) mode (also referred to herein as an enhanced mode). The memory modules can also be inserted in the sockets of the memory system in different configurations.

公开(公告)号：US11507280B2

公开(公告)日：2022-11-22

申请号：US16875881

申请日：2020-05-15

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Robert E. Palmer ,  John W. Poulton

IPC: G06F3/06 ,  G06F13/16 ,  G06Q10/00 ,  G11C7/02 ,  G11C11/406 ,  G06Q20/00

Abstract: A system includes a memory controller and a memory device having a command interface and a plurality of memory banks, each with a plurality of rows of memory cells. The memory controller transmits an auto-refresh command to the memory device. Responsive to the auto-refresh command, during a first time interval, the memory device performs refresh operations to refresh the memory cells and the command interface of the memory device is placed into a calibration mode for the duration of the first time interval. Concurrently, during at least a portion of the first time interval, the memory controller performs a calibration of a data interface circuit of the memory device. The auto-refresh command may specify an order in which memory banks of the memory device are to be refreshed, such that the memory device sequentially refreshes a respective row in the plurality of memory banks in the specified bank order.

公开(公告)号：US11502681B2

公开(公告)日：2022-11-15

申请号：US17296575

申请日：2019-11-27

Applicant: Rambus Inc.

Inventor： Talip Ucar ,  Frederick A. Ware

IPC: H03K17/56 ,  G06F1/10 ,  H03F3/04

Abstract: A transmitter merges even and odd data streams to drive a serialized signal. Identical even and odd drivers take turns driving symbols from respective even and odd streams using respective pull-up transistors and pull-down transistors. Each transistor exhibits a significant source-gate capacitance that is charged when the transistor is turned onto drive the serialized signal. Charging one of these capacitances loads the power supply and thus introduces noise. Each even and odd driver includes a pre-driver that times the charging of a source-gate capacitance in the active driver to the discharge of a source-gate capacitance in the inactive driver. The discharge of the source-gate capacitance in the inactive driver counters the effect of charging the active driver, providing much of the power required by the active driver and thus reducing supply noise.

公开(公告)号：US11487679B2

公开(公告)日：2022-11-01

申请号：US17081909

申请日：2020-10-27

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Amir Amirkhany ,  Suresh Rajan ,  Mohammad Hekmat ,  Dinesh Patil

IPC: G06F13/14 ,  G06F13/16 ,  G11C7/10 ,  G11C8/18 ,  G11C11/419 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/4093 ,  G11C11/4096 ,  G11C5/02 ,  G06F13/40 ,  G11C29/02

Abstract: A semiconductor memory system includes a first semiconductor memory die and a second semiconductor memory die. The first semiconductor memory die includes a primary data interface to receive an input data stream during write operations and to deserialize the input data stream into a first plurality of data streams, and also includes a secondary data interface, coupled to the primary data interface, to transmit the first plurality of data streams. The second semiconductor memory die includes a secondary data interface, coupled to the secondary data interface of the first semiconductor memory die, to receive the first plurality of data streams.

公开(公告)号：US11474957B2

公开(公告)日：2022-10-18

申请号：US17022746

申请日：2020-09-16

Applicant: Rambus Inc.

Inventor： Ian Shaeffer ,  Frederick A. Ware

IPC: G06F12/14 ,  G06F3/06 ,  G06F13/16 ,  G06F12/02

Abstract: A multi-rank memory system in which calibration operations are performed between a memory controller and one rank of memory while data is transferred between the controller and other ranks of memory. A memory controller performs a calibration operation that calibrates parameters pertaining to transmission of data via a first data bus between the memory controller and a memory device in a first rank of memory. While the controller performs the calibration operation, the controller also transfers data with a memory device in a second rank of memory via a second data bus.

公开(公告)号：US20220291848A1

公开(公告)日：2022-09-15

申请号：US17829207

申请日：2022-05-31

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Robert E. Palmer ,  John W. Poulton

IPC: G06F3/06 ,  G06F13/16 ,  G06Q10/00 ,  G11C7/02 ,  G11C11/406 ,  G06Q20/00

Abstract: A system includes a memory controller and a memory device having a command interface, refresh circuitry, control logic, and a plurality of memory banks, each with a plurality of rows of memory cells. The command interface is operable to receive a refresh command from a memory controller and the refresh circuitry is configured to perform one or more refresh operations to refresh data stored in at least one bank of the plurality of memory banks during a refresh time interval in response to the refresh command from the memory controller. The control logic is to configure the command interface to enter a calibration mode during the refresh time interval, and the command interface is configured to perform a calibration operation in the calibration mode during the refresh time interval.

公开(公告)号：US20220283941A1

公开(公告)日：2022-09-08

申请号：US17702505

申请日：2022-03-23

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  John Eric Linstadt ,  Christopher Haywood

IPC: G06F12/0804 ,  G06F12/12

Abstract: A hybrid volatile/non-volatile memory module employs a relatively fast, durable, and expensive dynamic, random-access memory (DRAM) cache to store a subset of data from a larger amount of relatively slow and inexpensive nonvolatile memory (NVM). A module controller prioritizes accesses to the DRAM cache for improved speed performance and to minimize programming cycles to the NVM. Data is first written to the DRAM cache where it can be accessed (written to and read from) without the aid of the NVM. Data is only written to the NVM when that data is evicted from the DRAM cache to make room for additional data. Mapping tables relating NVM addresses to physical addresses are distributed throughout the DRAM cache using cache line bits that are not used for data.

公开(公告)号：US20220262412A1

公开(公告)日：2022-08-18

申请号：US17665760

申请日：2022-02-07

Applicant: Rambus Inc.

Inventor： James E. Harris ,  Thomas Vogelsang ,  Frederick A. Ware ,  Ian P. Shaeffer

IPC: G11C7/10 ,  G11C7/08 ,  G11C5/02 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/4091 ,  G11C7/06 ,  G11C7/12 ,  G11C7/22 ,  G11C8/08 ,  G11C8/10

Abstract: Row activation operations within a memory component are carried out with respect to subrows instead of complete storage rows to reduce power consumption. Further, instead of activating subrows in response to row commands, subrow activation operations are deferred until receipt of column commands that specify the column operation to be performed and the subrow to be activated.

公开(公告)号：US20220253240A1

公开(公告)日：2022-08-11

申请号：US17608426

申请日：2020-04-28

Applicant: RAMBUS INC.

Inventor： Christopher Haywood ,  Frederick A. Ware

IPC: G06F3/06

Abstract: A cascaded memory system includes a memory module having a primary interface coupled to a memory controller via a first communication channel and a secondary interface coupled to a second memory module via a second communication channel. The first memory module buffers and repeats signals received on the primary and secondary interfaces to enable communications between the memory controller and the secondary memory module.

公开(公告)号：US20220221989A1

公开(公告)日：2022-07-14

申请号：US17586575

申请日：2022-01-27

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Ely Tsern

IPC: G06F3/06 ,  G11C5/04 ,  G11C7/10 ,  G06F12/06

Abstract: Memory modules, systems, memory controllers and associated methods are disclosed. In one embodiment, a memory module includes a module substrate having first and second memory devices. Buffer circuitry disposed on the substrate couples to the first and second memory devices via respective first and second secondary interfaces. The buffer circuitry includes a primary signaling interface for coupling to a group of signaling links associated with a memory controller. The primary signaling interface operates at a primary signaling rate and the first and second secondary data interfaces operate at a secondary signaling rate. During a first mode of operation, the primary interface signaling rate is at least twice the secondary signaling rate. A first time interval associated with a transfer of first column data via the first secondary interface temporally overlaps a second time interval involving second column data transferred via the second secondary interface.