公开(公告)号：US20220246598A1

公开(公告)日：2022-08-04

申请号：US17726222

申请日：2022-04-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Fa Chen ,  Chen-Hua Yu

IPC: H01L25/00 ,  H01L21/48 ,  H01L23/00 ,  H01L21/768 ,  H01L23/538 ,  H01L23/522 ,  H01L25/07

Abstract: Semiconductor devices are provided in which a first semiconductor device is bonded to a second semiconductor device. The bonding may occur at a gate level, a gate contact level, a first metallization layer, a middle metallization layer, or a top metallization layer of either the first semiconductor device or the second semiconductor device.

公开(公告)号：US20220223565A1

公开(公告)日：2022-07-14

申请号：US17337594

申请日：2021-06-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsien-Wei Chen ,  Ming-Fa Chen

IPC: H01L25/065 ,  H01L23/00 ,  H01L25/00

Abstract: Packages and methods of fabricating the same are provided. The package includes a first die, wherein the first die includes a plurality of through vias from a first surface of the first die toward a second surface of the first die; a second die disposed below the first die, wherein the second surface of the first die is bonded to the second die; an isolation layer disposed in the first die, wherein the plurality of through vias extend through the isolation layer; an encapsulation laterally surrounding the first die, wherein the encapsulation is laterally separated from the isolation layer; a buffer layer disposed over the first die, the isolation layer, and the encapsulation; and a plurality of conductive terminals disposed over the isolation layer, wherein the plurality of conductive terminals is electrically connected to corresponding ones of the plurality of through vias.

公开(公告)号：US20220223553A1

公开(公告)日：2022-07-14

申请号：US17315487

申请日：2021-05-10

Applicant: Taiwan Semiconductor Manufacturing Co, Ltd.

Inventor： Ming-Fa Chen ,  Hsien-Wei Chen ,  Sung-Feng Yeh ,  Jie Chen

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/00

Abstract: A semiconductor package includes a first semiconductor die, a second semiconductor die and a plurality of bumps. The first semiconductor die has a front side and a backside opposite to each other. The second semiconductor die is disposed at the backside of the first semiconductor die and electrically connected to first semiconductor die. The plurality of bumps is disposed at the front side of the first semiconductor die and physically connects first die pads of the first semiconductor die. A total width of the first semiconductor die may be less than a total width of the second semiconductor die.

公开(公告)号：US11373981B2

公开(公告)日：2022-06-28

申请号：US16786969

申请日：2020-02-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Fa Chen ,  Sung-Feng Yeh ,  Jian-Wei Hong

IPC: H01L25/065 ,  H01L23/60 ,  H01L21/683 ,  H01L23/00 ,  H01L25/00

Abstract: A package includes a first die, a second die, a first encapsulant, first through insulating vias (TIV), a second encapsulant, and second TIVs. The second die is stacked on the first die. The first encapsulant laterally encapsulates the first die. The first TIVs are aside the first die. The first TIVs penetrate through the first encapsulant and are electrically floating. The second encapsulant laterally encapsulates the second die. The second TIVs are aside the second die. The second TIVs penetrate through the second encapsulant and are electrically floating. The second TIVs are substantially aligned with the first TIVs.

公开(公告)号：US11322477B2

公开(公告)日：2022-05-03

申请号：US16896219

申请日：2020-06-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Fa Chen ,  Nien-Fang Wu ,  Sung-Feng Yeh ,  Tzuan-Horng Liu ,  Chao-Wen Shih

IPC: H01L25/065 ,  H01L23/538 ,  H01L25/00 ,  H01L21/56 ,  H01L21/683 ,  H01L23/00 ,  H01L23/544 ,  H01L23/31

Abstract: A structure including stacked substrates, a first semiconductor die, a second semiconductor die, and an insulating encapsulation is provided. The first semiconductor die is disposed over the stacked substrates. The second semiconductor die is stacked over the first semiconductor die. The insulating encapsulation includes a first encapsulation portion encapsulating the first semiconductor die and a second encapsulation portion encapsulating the second semiconductor die.

公开(公告)号：US11257787B2

公开(公告)日：2022-02-22

申请号：US16876140

申请日：2020-05-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsien-Wei Chen ,  Ming-Fa Chen ,  Sung-Feng Yeh

IPC: H01L23/02 ,  H01L25/065 ,  H01L21/56 ,  H01L23/498 ,  H01L23/31 ,  H01L23/00 ,  H01L23/48

Abstract: A package structure includes at least one semiconductor die, an insulating encapsulant, an isolation layer and a redistribution layer. The at least one first semiconductor die has a semiconductor substrate and a conductive post disposed on the semiconductor substrate. The insulating encapsulant is partially encapsulating the first semiconductor die, wherein the conductive post has a first portion surrounded by the insulating encapsulant and a second portion that protrudes out from the insulating encapsulant. The isolation layer is disposed on the insulating encapsulant and surrounding the second portion of the conductive post. The redistribution layer is disposed on the first semiconductor die and the isolation layer, wherein the redistribution layer is electrically connected to the conductive post of the first semiconductor die.

公开(公告)号：US20220020675A1

公开(公告)日：2022-01-20

申请号：US17135435

申请日：2020-12-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Fa Chen ,  Chin-Shyh Wang ,  Chao-Wen Shih

IPC: H01L23/498 ,  H01L21/768 ,  H01L21/762

Abstract: A method includes etching a substrate to form an opening, depositing a first dielectric liner extending into the opening, and depositing a second dielectric liner over the first dielectric liner. The second dielectric liner extends into the opening. A conductive material is filled into the opening. The method further includes performing a first planarization process to planarize the conductive material so that a portion of the conductive material in the opening forms a through-via, performing a backside grinding process on the substrate until the through-via is revealed from a backside of the substrate, and forming a conductive feature on the backside of the substrate. The conductive feature is electrically connected to the through-via.

公开(公告)号：US20220013480A1

公开(公告)日：2022-01-13

申请号：US16924216

申请日：2020-07-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Fa Chen ,  Chao-Wen Shih ,  Tzuan-Horng Liu ,  Jen-Li Hu

IPC: H01L23/00 ,  H01L23/64 ,  H01L23/522 ,  H01L21/768

Abstract: Provided is packages and methods of fabricating a package and. The method includes bonding a first device die with a second device die. The second device die is over the first device die. A bonding structure is formed in a combined structure including the first and the second device dies. A component is formed in the bonding structure. The component includes a passive device or a transmission line. The method further includes forming a first and a second electrical connectors electrically coupling to a first end and a second end of the component.

公开(公告)号：US20210391413A1

公开(公告)日：2021-12-16

申请号：US16901912

申请日：2020-06-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsien-Wei Chen ,  Ying-Ju Chen ,  Jie Chen ,  Ming-Fa Chen

IPC: H01L49/02 ,  H01L21/768 ,  H01G4/30 ,  H01L23/522

Abstract: Methods of forming a super high density metal-insulator-metal (SHDMIM) capacitor and semiconductor device are disclosed herein. A method includes depositing a first insulating layer over a semiconductor substrate and a series of conductive layers separated by a series of dielectric layers over the first insulating layer, the series of conductive layers including device electrodes and dummy metal plates. A first set of contact plugs through the series of conductive layers contacts one or more conductive layers of a first portion of the series of conductive layers. A second set of contact plugs through the series of dielectric layers avoids contact of a second portion of the series of conductive layers, the second portion of the series of conductive layers electrically floating.

公开(公告)号：US11164848B2

公开(公告)日：2021-11-02

申请号：US16737869

申请日：2020-01-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Fa Chen ,  Chao-Wen Shih ,  Min-Chien Hsiao ,  Sung-Feng Yeh ,  Tzuan-Horng Liu ,  Chuan-An Cheng

IPC: H01L25/065 ,  H01L23/48 ,  H01L25/00 ,  H01L23/31

Abstract: A semiconductor structure includes a stacked structure. The stacked structure includes a first semiconductor die and a second semiconductor die. The first semiconductor die includes a first semiconductor substrate having a first active surface and a first back surface opposite to the first active surface. The second semiconductor die is over the first semiconductor die, and includes a second semiconductor substrate having a second active surface and a second back surface opposite to the second active surface. The second semiconductor die is bonded to the first semiconductor die through joining the second active surface to the first back surface at a first hybrid bonding interface along a vertical direction. Along a lateral direction, a first dimension of the first semiconductor die is greater than a second dimension of the second semiconductor die.