公开(公告)号：US10523947B2

公开(公告)日：2019-12-31

申请号：US15721078

申请日：2017-09-29

Applicant: ATI Technologies ULC

Inventor： Ihab Amer ,  Boris Ivanovic ,  Gabor Sines ,  Yang Liu ,  Ho Hin Lau ,  Haibo Liu ,  Kyle Plumadore

IPC: H04N7/12 ,  H04N19/137 ,  H04N19/115 ,  H04N19/132 ,  H04N19/177 ,  A63F13/335

Abstract: Systems, apparatuses, and methods for encoding bitstreams of uniquely rendered video frames with variable frame rates are disclosed. A rendering unit and an encoder in a server are coupled via a network to a client with a decoder. The rendering unit dynamically adjusts the frame rate of uniquely rendered frames. Depending on the operating mode, the rendering unit conveys a constant frame rate to the encoder by repeating some frames or the rendering unit conveys a variable frame rate to the encoder by conveying only uniquely rendered frames to the encoder. Depending on the operating mode, the encoder conveys a constant frame rate bitstream to the decoder by encoding repeated frames as skip frames, or the encoder conveys a variable frame rate bitstream to the decoder by dropping repeated frames from the bitstream.

公开(公告)号：US20190394503A1

公开(公告)日：2019-12-26

申请号：US16561982

申请日：2019-09-05

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Lei Zhang ,  Gabor Sines ,  Khaled Mammou ,  David Glen ,  Layla A. Mah ,  Rajabali M. Koduri ,  Bruce Montag

IPC: H04N21/2343 ,  H04L29/06 ,  H04N21/2368 ,  H04N21/236 ,  H04N21/414 ,  H04N21/422 ,  H04N21/434 ,  H04N21/43 ,  H04N21/437

Abstract: Virtual Reality (VR) processing devices and methods are provided for transmitting user feedback information comprising at least one of user position information and user orientation information, receiving encoded audio-video (A/V) data, which is generated based on the transmitted user feedback information, separating the A/V data into video data and audio data corresponding to a portion of a next frame of a sequence of frames of the video data to be displayed, decoding the portion of a next frame of the video data and the corresponding audio data, providing the audio data for aural presentation and controlling the portion of the next frame of the video data to be displayed in synchronization with the corresponding audio data.

公开(公告)号：US10509666B2

公开(公告)日：2019-12-17

申请号：US15637810

申请日：2017-06-29

Applicant: ATI Technologies ULC

Inventor： Anthony Asaro ,  Yinan Jiang ,  Kelly Donald Clark Zytaruk

IPC: G06F9/46 ,  G06F9/455 ,  G06F9/48 ,  G06F9/38 ,  G06F21/74 ,  G06F13/372 ,  G06F21/53

Abstract: A register protection mechanism for a virtualized accelerated processing device (“APD”) is disclosed. The mechanism protects registers of the accelerated processing device designated as physical-function-or-virtual-function registers (“PF-or-VF* registers”), which are single architectural instance registers that are shared among different functions that share the APD in a virtualization scheme whereby each function can maintain a different value in these registers. The protection mechanism for these registers comprises comparing the function associated with the memory address specified by a particular register access request to the “currently active” function for the APD and disallowing the register access request if a match does not occur.

公开(公告)号：US10474490B2

公开(公告)日：2019-11-12

申请号：US15637800

申请日：2017-06-29

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Gongxian Jeffrey Cheng ,  Louis Regniere ,  Anthony Asaro

IPC: G06F9/50 ,  G06F9/46 ,  G06F9/455

Abstract: A technique for efficient time-division of resources in a virtualized accelerated processing device (“APD”) is provided. In a virtualization scheme implemented on the APD, different virtual machines are assigned different “time-slices” in which to use the APD. When a time-slice expires, the APD performs a virtualization context switch by stopping operations for a current virtual machine (“VM”) and starting operations for another VM. Typically, each VM is assigned a fixed length of time, after which a virtualization context switch is performed. This fixed length of time can lead to inefficiencies. Therefore, in some situations, in response to a VM having no more work to perform on the APD and the APD being idle, a virtualization context switch is performed “early.” This virtualization context switch is “early” in the sense that the virtualization context switch is performed before the fixed length of time for the time-slice expires.

公开(公告)号：US10445275B2

公开(公告)日：2019-10-15

申请号：US15582479

申请日：2017-04-28

Applicant: ATI Technologies ULC

Inventor： Nima Osqueizadeh

IPC: G06F13/40 ,  G06F13/16 ,  G06F13/42

Abstract: Described is a solid state graphics (SSG) subsystem including a die and a package, where the die includes a memory hub, graphics processing unit(s) (GPU(s)) connected to the memory hub, first memory architecture controller(s) connected to the memory hub and directly controlling access to first memory architecture(s), second memory architecture controller associated with each GPU and each second memory architecture controller connected to the memory hub and second memory architecture(s), an expansion bus first memory architecture controller connected to the memory hub and being an endpoint for a host system and an expansion bus controller coupled to the expansion bus first memory architecture controller and capable of connecting to the host system. The first memory architecture(s) and the second memory architecture(s) are either located on the SSG subsystem, located on the package, or a combination thereof.

公开(公告)号：US10346945B2

公开(公告)日：2019-07-09

申请号：US15901603

申请日：2018-02-21

Applicant: ATI Technologies ULC

Inventor： Laurent Lefebvre ,  Andrew Gruber ,  Stephen Morein

IPC: G06T1/00 ,  G06T1/20 ,  G06F9/38 ,  G06T15/00 ,  G06T15/04 ,  G06T1/60 ,  G09G5/00 ,  G09G5/36

Abstract: A graphics processing system comprises at least one memory device storing a plurality of pixel command threads and a plurality of vertex command threads. An arbiter coupled to the at least one memory device is provided that selects a pixel command thread from the plurality of pixel command threads and a vertex command thread from the plurality of vertex command threads. The arbiter further selects a command thread from the previously selected pixel command thread and the vertex command thread, which command thread is provided to a command processing engine capable of processing pixel command threads and vertex command threads.

公开(公告)号：US10324860B2

公开(公告)日：2019-06-18

申请号：US15695683

申请日：2017-09-05

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Anthony Asaro ,  Kevin Normoyle ,  Mark Hummel

IPC: G06F12/10 ,  G06F12/1036 ,  G06F12/08 ,  G06F12/06 ,  G06F12/02 ,  G06F12/109

Abstract: A method and system for allocating memory to a memory operation executed by a processor in a computer arrangement having a first processor configured for unified operation with a second processor. The method includes receiving a memory operation from a processor and mapping the memory operation to one of a plurality of memory heaps. The mapping produces a mapping result. The method also includes providing the mapping result to the processor.

公开(公告)号：US10268620B2

公开(公告)日：2019-04-23

申请号：US15389747

申请日：2016-12-23

Applicant: ATI Technologies ULC

Inventor： Nima Osqueizadeh

IPC: G06F3/00 ,  G06F13/38 ,  G06F13/40 ,  G06F13/16

Abstract: Described herein are apparatus for connecting a first memory architecture locally to a graphics processing unit (GPU) through a local switch, where the first memory architecture can be a non-volatile memory (NVM) or other similarly used memories, for example, along with associated controllers. The apparatus includes the GPU(s) or discrete GPU(s) (dGPU(s)) (collectively GPU(s)), second memory architectures associated with the GPU(s), the local switch, first memory architecture(s), first memory architecture controllers or first memory architecture connector(s). In an implementation, the local switch is part of the GPU. The apparatus can also include a controller for distributing a large transaction among multiple first memory architectures. In an implementation, the first memory architectures can be directly connected to the GPU. In an implementation, the apparatus is user configurable. In an implementation, the apparatus is a solid state graphics (SSG) card.

公开(公告)号：US10218273B2

公开(公告)日：2019-02-26

申请号：US15632765

申请日：2017-06-26

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Erhan Ergin ,  Dipanjan Sengupta ,  Elsie Lo ,  Stephen V. Kosonocky ,  Sree Rajesh Saha ,  Divya Guruja

IPC: H02M3/158

Abstract: A distributed voltage regulator has switches that function as resistors and are distributed in rows in a grid pattern across a regulated voltage domain. The switches receive an unregulated voltage and supply the regulated voltage. Switch control lines selectively enable the switches to achieve the desired voltage regulation. Droop detect circuits are also distributed through regulated voltage domain. The droop detect circuits detect when the regulated voltage is below a threshold and supply droop detect signals indicative thereof. A plurality of select circuits receive a first group of control lines to configure the switches for charge injection in response to a droop condition and a second group of control lines to configure the switches for other voltage regulation. The select circuits select one of the first and second group of control lines as switch control lines to configure the switches based on the droop detect signals.

公开(公告)号：US10198358B2

公开(公告)日：2019-02-05

申请号：US14243050

申请日：2014-04-02

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Angel E. Socarras ,  Kostantinos Danny Christidis ,  Curtis Alan Gilgan ,  Alexander Fuad Ashkar

IPC: G06F12/0875 ,  G06F11/22 ,  G06F11/30 ,  G06F11/273

Abstract: Apparatuses, computer readable mediums, and methods of processor unit testing using cache resident testing are disclosed. The method may include loading a test program in a cache on a chip comprising one or more processor units. The method may include the one or more processor units executing the test program to generate one or more results. The method may include redirecting a first memory reference to the cache, wherein the first memory reference is generated during the execution of the test program. The method may include determining whether the one or more generated results match one or more test results. The method may include redirecting a memory request to a memory location resident in the cache if the memory request includes a memory location not resident in the cache. The method may include redirecting a memory request to the cache if the memory request is not directed to the cache.